如何避免Makefile中重复的隐式规则?
我正在开发一个Makefile自动生成软件(CodeMate),我想知道我是否可以避免为不同的文件编写隐式规则就足够了,但具有相同的操作:
%.o: %.F90
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c $< $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
%.o: %.f90
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c $< $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
%.o: %.F
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c $< $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
%.o: %.f
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c $< $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
这可以很好地工作,但有点难看。
谢谢!
I am working on a Makefile auto-generating software (CodeMate), and I would like to know if I can avoid to write the implicit rules for different file suffices but with the same operations as:
%.o: %.F90
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c lt; $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
%.o: %.f90
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c lt; $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
%.o: %.F
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c lt; $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
%.o: %.f
@echo " Creating dependency $@"
@echo $(seperator)
@$(FORTRAN_COMPILER) -c lt; $(OPTION) $(FORTRAN_FLAGS) $(INCLUDES)
This can work well, but is a little ugly.
Thanks!
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