x86 上的两个后续 CPU 存储是否刷新到缓存并保持顺序？
假设有两个线程分别运行在 x86 CPU0 和 CPU1 上。运行在 CPU0 上的线程执行以下命令：
A=1
B=1
包含 A 的高速缓存行最初由 CPU1 拥有，而包含 B 的高速缓存行由 CPU0 拥有。
我有两个问题：
如果我理解正确的话，两个存储都会被放入CPU的存储缓冲区中。然而，对于第一个存储
A=1，CPU1 的缓存必须失效，而第二个存储B=1可以立即刷新，因为 CPU0 拥有包含它的缓存行。我知道 x86 CPU 尊重商店订单。这是否意味着B=1不会在A=1之前写入缓存？假设在 CPU1 中执行以下命令：
同时(B=0);
打印A
在CPU1中的while和print命令之间只添加lfence是否足够，而不在A=1和之间添加sfence CPU0 中的 B=1 以便在 x86 上始终打印出 1？
while (B=0);
lfence
print A
Assume there are two threads running on x86 CPU0 and CPU1 respectively. Thread running on CPU0 executes the following commands:
A=1
B=1
Cache line containing A initially owned by CPU1 and that containing B owned by CPU0.
I have two questions:
If I understand correctly, both stores will be put into CPU’s store buffer. However, for the first store
A=1the cache of CPU1 must be invalidated while the second storeB=1can be flushed immediately since CPU0 owns the cache line containing it. I know that x86 CPU respects store orders. Does that mean thatB=1will not be written to the cache beforeA=1?Assume in CPU1 the following commands are executed:
while (B=0);
print A
Is it enough to add only lfence between the while and print commands in CPU1 without adding a sfence between A=1 and B=1 in CPU0 to get 1 always printed out on x86?
while (B=0);
lfence
print A
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（1）
在 x86 中，所有处理器都会以相同的顺序观察单个处理器的写入。在您的示例中以及 x86 上的任何正常程序中都不需要进行隔离。您的程序：
缓存中到底发生了什么是特定于模型的。缓存中可能会发生各种技巧和推测行为，但可观察到的行为始终遵循规则。
请参阅英特尔系统编程指南第 3 卷第 8.2.2 节。有关内存排序的详细信息。
In x86, writes by a single processor are observed in the same order by all processors. No need to fence in your example, nor in any normal program on x86. Your program:
What exactly happens in cache is model specific. All kinds of tricks and speculative behavior can occur in cache, but the observable behavior always follows the rules.
See Intel System Programming Guide Volume 3 section 8.2.2. for the details on memory ordering.