我想使用arm-linux-gcc编译器套件[arm-linux-gcc (Buildroot 2011.08) 4.3.6]交叉编译一个用于ARM架构的简单程序。我尝试使用一个简单的 makefile 来编译 C 代码，并使用另一个简单的 makefile 来编译 C++ 代码。例如，我的 C 代码 makefile 复制如下，但它不会创建在我的嵌入式系统上运行的 ELF 二进制文件。主机系统是 x64 GNU Linux。
下面是我的 C 程序的非常简单的 makefile 的列表：
CC=arm-linux-gcc
CFLAGS=-Wall
main: test.o
clean:
rm -f test test.o
上面复制的 makefile 只创建一个扩展名为 .o 的目标文件，并且不创建 ELF 二进制文件。
我在 Google 上搜索了一个好的解决方案，但我似乎找不到一个网页显示 C 和 C++ 程序的交叉编译 ARM makefile 示例。也许这篇文章的答案可以展示这样的例子。
I would like to cross-compile a simple program for ARM architecture using the arm-linux-gcc suite of compilers [arm-linux-gcc (Buildroot 2011.08) 4.3.6]. I've attempted to use a simple makefile for compiling C code, and another simple makefile for compiling C++ code. For example, my makefile for C code is reproduced below, but it does not create an ELF binary for running on my embedded system. The host system is x64 GNU Linux.
Here is the listing of my very simple makefile for a C program:
CC=arm-linux-gcc
CFLAGS=-Wall
main: test.o
clean:
rm -f test test.o
The makefile reproduced above only creates an object file with extension .o, and does not create an ELF binary.
I've Googled for a good solution, but I can't seem to find one webpage showing example cross-compile ARM makefiles for both C and C++ programs. Perhaps an answer to this post could show such examples.
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查看 GNU make 手册 (
info make)，第 10.2 节。它有一个隐式规则的目录，即您不需要显式声明命令的规则。就像 @GregHewgill 所想的那样，“链接单个目标文件”隐式规则从No构建N，但名称必须匹配。因此，您可以将可执行文件命名为目标文件，在这种情况下，或者（更标准，因为它定义了
all目标）完全足够了。您还可以明确地写出规则，就像 Greg Hewgill 也描述的那样。在这种情况下，标准规则是：
在 Makefile 中包含 LDFLAGS 和 LDLIBS，这会让用户的生活更轻松。
（原文如此：我认为 LOADLIBES 确实是 LOADLIBS，作者漏掉了
-o）。总的来说，我建议使用
autoconf和automake而不是手动生成 makefile。为您提供了一堆 Makefile 功能，只需很少的工作。Have a look at the GNU make manual (
info make), Section 10.2. It has a catalogue of the implicit rules, i.e. the rules where you don't need to explicitly state the commands. Like @GregHewgill thought, the "Linking a single object file" implicit rule buildsNfromN.o, but the name must match. Therefore, you can either name your executable like your object file, in which caseor (more standard because it defines the
alltarget)completely suffice. You can also write out the rule explicitly, like Greg Hewgill also described. In this case, the standard rule is:
Include the LDFLAGS and LDLIBS in your Makefile, it makes life easier for users.
(sic: I think LOADLIBES is really LOADLIBS, and the author missed the
-o).Overall, I'd recommend
autoconfandautomakeinstead of hand-rolling makefiles. Gives you a bunch of Makefile features for very little work.我尝试了您的
Makefile并更改了以下内容：它在更改后工作并创建了一个名为
test的二进制文件。似乎有一些隐式规则知道如何链接whatever（如果其依赖项之一是whatever.o）。另一种方法是显式列出规则：
这使用特殊宏
$@（表示 target）和$$（表示 target） >依赖项）。I tried your
Makefileand changed the following:It worked after this changed and created a binary called
test. It seems that there is some implicit rule that knows how to linkwhateverif one of its dependencies iswhatever.o.Another way is to list the rule explicitly:
This uses the special macros
$@(which means target) and$$(which means dependencies).