Spartan 3 入门套件约束文件
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我在编写约束文件时遇到了一个小问题斯巴达 3 入门套件。
我已经阅读了 Xilinx（制造商）提供的文档，并且在网上搜索了几个星期，但没有任何运气。
我想要做的是将我的网表接口链接到板上的任何 3 个 40 针接头。 （参见下图）
通常它非常简单，如果我想连接一个按钮或一个 LED板上，我只是读取板上的连接名称，例如其中一个按钮是 M13 并在 UCF 文件中写入如下内容：
NET "BTN0" LOC = "M13";
正如您在图像上看到的，标题被命名为 A1 、A2 和 B1 上但奇怪的是，以下方法均不起作用：
NET "TestOutputLine" LOC = "A1(0)"; -- The (0) is to reference a single line on an array
NET "TestOutputBus" LOC = "A1"; -- The bus is of equal dimension of A1 (which is 40)
我得到的错误意味着目标（由 LOC 指定）不存在或分配无效。
我希望你对我有一些想法。 提前致谢
编辑： 这是 ISE 的输出：
ConstraintSystem:59 - Constraint <NET "TestOutputBus" LOC = "A1";>
[circuit.ucf(12)]: NET "TestOutputBus" not found. Please verify that:
1. The specified design element actually exists in the original design.
但我非常确定 TestOutputBus 存在，事实上，我的设计中现在没有其他内容，并且正在使用正确的顶级单元。
编辑2： 我更新了我的 UCF 文件，现在是这样的：
NET "TestOutputBus(0)" LOC = "A1(0)";
NET "TestOutputBus(1)" LOC = "A1(1)";
但是我现在在映射中遇到了不同的错误：
MapLib:30 - LOC constraint A1:0 on TestOutputBus<0> is invalid: No such
site on the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
MapLib:30 - LOC constraint A1:1 on TestOutputBus<1> is invalid: No such
site on the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
解决方案：
为了将引脚 5 和 6 映射到 TestOutputBus(0) 和 TestOutputBus(1) ）分别我必须使用的是：
NET "TestOutputBus(0)" LOC = "N7"; -- A1 pin 5
NET "TestOutputBus(1)" LOC = "L5"; -- A1 pin 6
请注意，引脚 0 不可映射，这就是我使用引脚 5 和 6 的原因，以下表格显示了所有标头及其可映射引脚LOC。
I am not sure if this is the right stack exchange website to post this on, but if it isn't please move it to the appropriate one.
I am facing a small problem in writing my constraints file for the spartan 3 starter kit.
I have read the documentation provided by Xilinx (the manufacturer) and ive been searching online for a few weeks without any luck.
What i am trying to do is link my Netlist interface to any of the 3 40-pin-headers on the board. (See image below)
Usually its very simple, if say i want to interface a button or a led on the board, i just read the connection name on the board, for example one of the buttons is M13 and write in the UCF file something like this :
NET "BTN0" LOC = "M13";
As you can see on the image the headers are named A1, A2 and B1 on the board, but oddly enough, none of the following worked :
NET "TestOutputLine" LOC = "A1(0)"; -- The (0) is to reference a single line on an array
NET "TestOutputBus" LOC = "A1"; -- The bus is of equal dimension of A1 (which is 40)
The errors i got meant that either the target (specified by LOC) does not exist or that the assignment is invalid.
I hope you have some ideas for me.
Thanks in advance
EDIT :
Here is the output from ISE :
ConstraintSystem:59 - Constraint <NET "TestOutputBus" LOC = "A1";>
[circuit.ucf(12)]: NET "TestOutputBus" not found. Please verify that:
1. The specified design element actually exists in the original design.
But i am pretty sure that TestOutputBus exists, as a matter of fact there is nothing else in my design right now, and the correct top level unit is being used.
EDIT2 :
I updated my UCF file, right now it's like this :
NET "TestOutputBus(0)" LOC = "A1(0)";
NET "TestOutputBus(1)" LOC = "A1(1)";
But i get a different error now in mapping :
MapLib:30 - LOC constraint A1:0 on TestOutputBus<0> is invalid: No such
site on the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
MapLib:30 - LOC constraint A1:1 on TestOutputBus<1> is invalid: No such
site on the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
Solution :
In order to get the pins 5 and 6 mapped to TestOutputBus(0) and TestOutputBus(1) respectively what i had to use was this :
NET "TestOutputBus(0)" LOC = "N7"; -- A1 pin 5
NET "TestOutputBus(1)" LOC = "L5"; -- A1 pin 6
Note that pins 0 are not mappable thats why i used pins 5 and 6, here are the tables that show the mappable pins for all headers and their LOCs.
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事实证明，FPGA 的每个接头的每个可用引脚都有一个地址。
数据表 (http://forums.xilinx.com/xlnx/attachments/xlnx/Spartan/3411/1/S3BOARD_RM.pdf) 很有帮助，尤其是第 49 - 51 页
As it turns out, there is an address for each usable pin of each header of the FPGA.
The datasheet (http://forums.xilinx.com/xlnx/attachments/xlnx/Spartan/3411/1/S3BOARD_RM.pdf) was helpful especially pages 49 - 51
我将之前的评论中的内容复制到您的问题中，因此这将是一个实际的答案，而不仅仅是评论。
您应该在 UCF 文件中为顶级模块上的每个端口设置 LOC 约束。因此，如果您有一个 40 位宽的总线作为顶层的输入或输出，那么您的 UCF 文件中还应该有 40 个单独的 LOC 约束，以确保顶层原理图中的逻辑总线实际上被映射到FPGA 上的正确引脚。如果您仅使用两个引脚，则可以将总线声明为 2 位宽并使用 2 个 LOC 约束。 FPGA 会将所有未使用的引脚视为输入并忽略它们。
I copied this from my earlier comment to your question so it would be an actual answer and not just a comment.
You should have LOC constraints in your UCF file for every port on your top-level module. So if you have a 40-bit-wide bus as an input or output at the top level then you should also have 40 separate LOC constraints in your UCF file to make sure that the logical bus in your top-level schematic actually gets mapped to the correct pins on your FPGA. If you are only using two pins, then you can declare the bus to be 2-bits wide and use 2 LOC constraints. The FPGA will treat all unused pins as inputs and ignore them.
当我不小心选择我的模块之一作为顶级模块时，我曾经遇到过原始的 ConstraintSystem:59 net xyz not find 错误。在错误模块的端口声明中找不到 UCF 中声明的引脚。
当我在 UCF 中声明了一些引脚但在顶部模块的端口声明中忽略它时，我也会收到此错误。
I once got the original ConstraintSystem:59 net xyz not found error when i accidentally selected one of my modules as a top module. The pins declared in UCF could not be found in the port declaration of wrong module.
Also i get this error when i have some pin declared in UCF but ommit it in port declaration of top module.