进程语法错误

发布于 2024-12-23 07:53:11 字数 3310 浏览 0 评论 0原文

我正在尝试模拟我的小程序,但不断收到错误消息,但我无法弄清楚原因。

错误消息是:

line 131 error near process

line 132 error near behavioral ; expected type void

行:

 130    end if;
 131    end process;
 132        end Behavioral;

我已经尝试解决这些问题几个小时,但我仍然没有任何线索。

整个代码:

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kuutonen is
    Port ( A1 : in  STD_LOGIC;
           B1 : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           A : out  STD_LOGIC;
           B : out  STD_LOGIC;
           C : out  STD_LOGIC;
           D : out  STD_LOGIC;
           E : out  STD_LOGIC;
           F : out  STD_LOGIC;
           G : out  STD_LOGIC);
end kuutonen;

architecture Behavioral of kuutonen is
    signal tmp : std_logic_vector (2 downto 0);
begin

    process (clk)
    begin
        if(tmp = "110")then
            tmp <= "000";
         end if;

        if (A1 = '0' and B1 = '0') then
            if (tmp ="000") then
                A <= '1';
                B <= '0';
                C <= '0';
                D <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                tmp <= tmp + 1;
            end if;

            if (tmp ="001")then
                B <= '1';
                A <= '0';
                C <= '0';
                D <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                tmp <= tmp + 1;
            end if;

            if (tmp ="010")then
                C <= '1';
                B <= '0';
                A <= '0';
                D <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                tmp <= tmp + 1;
            end if;

            if (tmp ="011")then
                D <= '1';
                B <= '0';
                C <= '0';
                A <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                E <= '1';

                if (tmp ="100")then
                    E <= '1';
                    B <= '0';
                    C <= '0';
                    D <= '0';
                    A <= '0';
                    F <= '0';
                    G <= '0';
                    tmp <= tmp+1;
                end if;

                if (tmp ="101")then
                    F <= '1';
                    B <= '0';
                    C <= '0';
                    D <= '0';
                    E <= '0';
                    A <= '0';
                    G <= '0';
                    tmp <= tmp+1;
                end if;

                if (tmp ="110")then
                    G <= '1';
                    B <= '0';
                    C <= '0';
                    D <= '0';
                    E <= '0';
                    F <= '0';
                    A <= '0';
                end if;

        end if;
    end process;
end Behavioral;

I am trying to simulate my small program and I keep getting error messages and I have not been able to figure out why.

The error messages are:

line 131 error near process

line 132 error near behavioral ; expected type void

The lines:

 130    end if;
 131    end process;
 132        end Behavioral;

I have tried to solve these for hours and I still do not have any clue.

Whole code:

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kuutonen is
    Port ( A1 : in  STD_LOGIC;
           B1 : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           A : out  STD_LOGIC;
           B : out  STD_LOGIC;
           C : out  STD_LOGIC;
           D : out  STD_LOGIC;
           E : out  STD_LOGIC;
           F : out  STD_LOGIC;
           G : out  STD_LOGIC);
end kuutonen;

architecture Behavioral of kuutonen is
    signal tmp : std_logic_vector (2 downto 0);
begin

    process (clk)
    begin
        if(tmp = "110")then
            tmp <= "000";
         end if;

        if (A1 = '0' and B1 = '0') then
            if (tmp ="000") then
                A <= '1';
                B <= '0';
                C <= '0';
                D <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                tmp <= tmp + 1;
            end if;

            if (tmp ="001")then
                B <= '1';
                A <= '0';
                C <= '0';
                D <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                tmp <= tmp + 1;
            end if;

            if (tmp ="010")then
                C <= '1';
                B <= '0';
                A <= '0';
                D <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                tmp <= tmp + 1;
            end if;

            if (tmp ="011")then
                D <= '1';
                B <= '0';
                C <= '0';
                A <= '0';
                E <= '0';
                F <= '0';
                G <= '0';
                E <= '1';

                if (tmp ="100")then
                    E <= '1';
                    B <= '0';
                    C <= '0';
                    D <= '0';
                    A <= '0';
                    F <= '0';
                    G <= '0';
                    tmp <= tmp+1;
                end if;

                if (tmp ="101")then
                    F <= '1';
                    B <= '0';
                    C <= '0';
                    D <= '0';
                    E <= '0';
                    A <= '0';
                    G <= '0';
                    tmp <= tmp+1;
                end if;

                if (tmp ="110")then
                    G <= '1';
                    B <= '0';
                    C <= '0';
                    D <= '0';
                    E <= '0';
                    F <= '0';
                    A <= '0';
                end if;

        end if;
    end process;
end Behavioral;

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私藏温柔 2024-12-30 07:53:11

仅从检查来看,我想说这可能是由于缺少“end if;” tmp=001 和 tmp=100 的情况之间。

Just from inspection, I'd say it's probably due to a missing "end if;" between the case for tmp=001 and tmp=100.

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