语言与 FPGA 有何关系？
我相信在大学时我为 FPGA 编写了一个程序，该程序是使用 C 语言派生的。我了解 VHDL 和 verilog 等语言。然而，我不明白的是程序员对于使用哪个有多少选择？它依赖于FPGA吗？我将使用 Xilinx FPGA。
我很困惑，因为 C 变体语言与 C 毫不奇怪，但我知道 VHDL 之类的东西与 C 完全不同。因此，如果我有选择，我更愿意使用 C 变体语言对 FPGA 进行编程。 Xilinx 网站上有一百万份文档，但内容并不太清晰。
I believe at university I wrote a program for an FPGA which was in a language derived from C. I am aware about languages such as VHDL and verilog. However, what I dont understand is the amount of choice a programmer has regarding which to use? Is it dependent on the FPGA? I am going to be using a Xilinx FPGA.
I am confused because the C-variant language was, unsurprisingly, similar to C- however I know things like VHDL are nothing like C. Therefore if I have a choice I would prefer to programme an FPGA using a C-variant language. The Xilinx website had a million documents and it wasn't overly clear.
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您使用的可能是 Verilog。它的很多结构都与 C 类似。我不会说它“像 C”，但有些语法是相似的。
VHDL 基于 ADA，所以是的，它是相当不同的。
有一些小型 FPGA 专用语言，但 VHDL 和 Verilog 是最主要的两种语言。我想其他大多数人现在都已经死了。
请记住，编写硬件和编写软件是两件完全不同的事情。您无法用 C (*) 这样的语言真正描述硬件构造。该语言需要具有特殊功能，以便您能够准确地描述您想要的内容。代码的结构需要能够提高硬件的效率。不要自欺欺人地认为只需更改语言/编译器就可以将一个软件神奇地运行在 FPGA 上。 （这更多是针对您向马蒂提出的后续问题）。
尝试使用 C 语言编写电路描述，就像尝试用英语对计算机进行编程一样。你可以做到，但是这确实是不适合这项工作的语言。
(*) 是的，我知道有 SystemC（一个 C++ 类库，旨在使代码可综合），但我还没有看到有人从中获得好的结果，当然在 FPGA 上也没有。即使这样，代码的结构也必须与 HDL 类似。
It was probably Verilog that you used. It's rather C-like in a lot of it's constructs. I wouldn't say it's "like C", but some syntax is similar.
VHDL is based on ADA, so yes, it's rather different.
There are some small FPGA specific languages around, but VHDL and Verilog are the big two. I think most others have died now.
Remember that writing hardware and writing software are two rather different things. You can't really describe hardware constructs in a language like C (*). The language needs to have special features to allow you to describe exactly what you want. The code needs to be structured in a way that will make the hardware efficient. Don't fool yourself into thinking that you can take a piece of software and magically run it on an FPGA just by changing the language/compiler. (This is targeted more at your follow up question to Marty).
Trying to use C to write a circuit description, is like trying to program a computer in English. You could do it, but it's really the wrong language for the job.
(*) Yes, I know there's SystemC (a C++ class library that is meant to make code synthesisable), but I've yet to see anyone get good results from it, and certainly not on FPGAs. Even then the code has to be structured in a similar way as for an HDL.
显然，在对 FPGA 进行编程时 HDL 仍然更可取（Xilinx、Altera 等：都接受 VHDL 或 Verilog）。
然而，事情正在发生变化（缓慢地）：现在有优秀的所谓的行为合成器，它们允许您用 C 语言编码并生成硬件，并在寄存器传输级别以 VHDL 或 Verilog 表示。它们有时被称为 HLS：高级综合。
问题是它们非常昂贵。
在学术层面：
基本上，这些工具通过提取依赖关系图来工作从C 程序：节点代表计算，边代表变量：这就是您在使用 C 或其他编程语言进行编程时所做的全部工作。使用这种内部表示，编译器可以进行与硬件相关的转换，例如：寄存器分配（将变量映射到寄存器，或将它们保持组合，即在线上）、操作调度（决定操作是否在同一时钟周期中执行）等，最后生成 HDL自动地。
希望这对
JCLL有帮助
Clearly HDL are still preferable when programming FPGA (Xilinx, Altera etc : all accept VHDL or Verilog).
However, things are changing (slowly) : there are now excellent so-called behavioral synthesizers that allow you to code in C and generate hardware, expressed for you in VHDL or Verilog at the register-transfer level. They are sometimes refered as HLS : high-level synthesis.
The problem is that they are quite expensive.
At the academic level :
Basically, these tools work by extracting a dependency graph from the C program : nodes represents computations and edges represent variables : that is all what you do when you program, in either C or other programming language. Using this internal representation, the compiler can do hardware-relevant transformations like : register allocation (mapping variables to register, or keeping them combinatorial i.e on wires), operations scheduling (deciding if operation execute in same clock cycle) etc, and finally generate HDL automatically.
Hope this helps
JCLL
通常 FPGA 供应商会提供同时支持 Verilog 和 VHDL 的工具链 - 由您选择您想要的语言。通常只支持这两种语言。
对于更多类似 C 的语言，一个不太可能的选择是使用 SystemC 的可综合子集。这是添加了电路友好的东西的 C++。我不确定 FGPA 工具是否支持这一点。
Usually FPGA vendors will have toolchains that support both Verilog and VHDL - it's up to you to choose which language you'd like. It's generally just these two languages that are supported.
For more C-like languages, a long-shot option is to use the synthesisable subset of SystemC. This is C++ with circuit-friendly stuff added. I'm not sure if the FGPA tools support this though.