VHDL MIPS 5级管道错误
该代码太长，无法发布，所以我只是描述它。我已经创建了一个几乎可以工作的 5 级 mips 管道。问题是到达指令解码阶段的每条 lw 指令都会覆盖执行阶段的控制信号值。不仅如此，它会导致PC跳过can指令，即从300 -> 300。 308. 我只需要知道在哪里寻找错误，因为这是课堂作业。如果我们去掉所有 LW 指令，CPU 就能正常工作。
例子： EX 阶段的加法器将低于 $4 $1 $2，应该是 1 一旦 LW 进入 ID 阶段，ALUsrc 就被置位，并且 ALUop 从减法变为加法 这迫使 EX 阶段的加法器添加 $4 $1 $2，导致 5 存储在 $4 中
The code for this is too long to post so Ill just describe it. I've created a 5 stage mips pipe that almost works. The catch is that EVERY lw instruction that reaches the instruction decode stage overwrites the control signal values in the execution stage. Not only that it causes the PC to skip can instruction, i.e from 300 -> 308. I just need some idea on where to look for bugs since this is a class assignment. If we take out all the LW instructions the CPU works fine.
Example:
The adder in the EX stage is going to sub $4 $1 $2 which should be 1
Once LW enters the ID stage ALUsrc is asserted AND ALUop is changed from subtract to add
This forces the adder in the EX stage to add $4 $1 $2 resulting in 5 being stored in $4
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http://en.wikipedia.org/wiki/File:MIPS_Architecture_% 28Pipelined%29.svg
MIPS 5 级管道（注释为显示写入寄存器选择和启用）
管道级的底线代表寄存器文件写（后）端口地址和写使能，WB 是来自存储器的数据。
http://www.mrc.uidaho.edu/mrc/ people/jff/digital/MIPSir.html
加载字指令
描述：
一个字从指定地址加载到寄存器中。
操作：$t = MEM[$s + offset]; advance_pc (4);
语法：lw $t, offset($s)
编码：
1000 11ss ssst tttt iiii iiii iiii iiii
其中写入寄存器地址 ($t) 输入是从由寄存器文件寄存器 $s 偏移量组成的数据存储器地址读取的，其中立即值 i 得到符号扩展。您的 $4 是上面的 $t，$1 或 $2 是 $s，而剩余的寄存器文件输出通道听起来是为了符号扩展立即数而被收买。
从您的描述来看，您似乎没有使用三端口寄存器文件，其中一个端口是只写端口。
对于三端口寄存器文件，唯一遇到冲突的情况是在从内存读取新的寄存器文件值并将其写入寄存器文件之前尝试使用内存中的新寄存器文件值。这可以通过编译器调度 NOOP 来管理，直到当后续指令尝试使用未完成的寄存器文件写入时退出，或者当其输出包含对未完成的寄存器文件写入的引用时，在硬件中停止 IF/ID。
IF/ID 右侧可以运行 3 条指令，每条指令都具有写入寄存器文件地址和写入使能。您需要将两个指令解码寄存器文件地址与所有三个地址进行比较，并停止 IF/ID，直到这些地址清除为止。存储在这三个流水线级中的每一个中的写使能用于确定是否应该比较这些流水线级中的写寄存器地址。
由于 ID/EX、EX/MEM 和 MEM/WB 写入寄存器文件地址未在其他任何地方使用，因此用于进行比较的电路可以与 IF/ID 和寄存器文件并置，从而防止影响最小时钟周期的不必要的布局延迟。
使用两端口寄存器文件要简单得多，并且推断 IF/ID 会停止，直到写入使能从 MEM/WB 返回，从而有效地将任何内存读取指令转换为 3 个周期指令（或更多，如果数据存储器是高速缓存或速度较慢，则数据内存可能会停止） ）。出于性能原因，它或多或少需要三端口寄存器文件。当 IF/ID 停止时（对于内存 -> 寄存器文件），存在一个隐含的多路复用器，用于从 MEM/WB 级获取两个寄存器文件端口控制（写入使能、写入地址）中的至少一个。
数据内存访问可能会导致 MEM/WB 停顿，就像指令内存访问也会导致 IF/ID 停顿一样。停滞的 IF/ID 不会向 ID/EX 发出寄存器文件的写使能，停滞的 MEM/WB 也不会。
http://en.wikipedia.org/wiki/File:MIPS_Architecture_%28Pipelined%29.svg
The MIPS 5 Stage Pipeline (annotated to show Write Reg Select and enable)
The bottom line through the pipeline stages represents the register file write (back) port address and write enable and WB is the data from memory.
http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html
Load Word Instruction
Description:
A word is loaded into a register from the specified address.
Operation: $t = MEM[$s + offset]; advance_pc (4);
Syntax: lw $t, offset($s)
Encoding:
1000 11ss ssst tttt iiii iiii iiii iiii
Where the write register address ($t) input is read from data memory address comprised of register file register $s offset with the immediate value i which gets sign extended. Your $4 is $t above, $1 or $2 is $s while the remaining register file output lane sounds to be suborned for the sign extended immediate.
From your description it sounds like you aren't using a three port register file with one port a write only port.
With a three port register file the only time you run into conflicts is when you attempt to use the new register file value from memory before it is read from memory and written to the register file. That can be managed by a compiler scheduling NOOPs until the outstanding register file write is retired when a following instruction is trying to use it, or stalling the IF/ID in hardware when it's output contains a reference to an outstanding register file write.
There are three instructions that can be in flight to the right of IF/ID, each with a write to register file address and a write enable. You'd need to compare both instruction decode register file addresses to all three of those and stall IF/ID until those clear out. The write enable stored in each of those three pipeline stages are used to determine whether the write register address in those pipeilne stages should be compared.
Because the ID/EX, EX/MEM and MEM/WB write register file addresses are not used anywhere else the circuitry for doing the comparison can be collocated with IF/ID and the Register File, preventing unnecessary layout delays affecting the minimum clock cycle.
Using a two port register file is much simpler and infers IF/ID stalling until the write enable comes back from MEM/WB, effectively turning any memory reading instructions into 3 cycle instructions (or more, data memory can stall if it's a cache or slow). It makes a three port register file more or less necessary for performance reasons. There's an implied multiplexer to source for at least one of the two register file port controls (write enable, write address) from the MEM/WB stage when IF/ID is stalled (for memory->regfile).
Data memory access can stall MEM/WB, just like instruction memory access can also stall IF/ID. A stalled IF/ID doesn't issue a write enable for the register file to ID/EX nor does a stalled MEM/WB.