CPU 每秒指令数
我在即将进行的测试的学习指南中收到了这个问题。我不明白如何解决这个问题。我的测试是今天，我希望得到一些帮助。
如果 CPU 每条指令发出一个内存请求，并且计算机以 200 MIPS 运行，那么大约需要多少个 CPU 才能使 400-MHZ 总线饱和？假设内存引用需要一个总线周期。现在，在使用缓存且缓存命中率为 90% 的系统中重复此问题。最后，需要多少缓存命中率才能允许 32 个 CPU 共享总线而不会使总线过载？
I was given this question on my study guide for a test I have coming up. I don't understand how to tackle this problem. My test is today and I would appreciate some help.
If a CPU issues one memory request every instruction and the computer runs at 200 MIPS, about how many CPUs will it take to saturate a 400-MHZ bus? Assume a memory reference requires one bus cycle. Now repeat this problem for a system in which caching is used and the caches have a 90% hit rate. Finally, what cache hit rate would be needed to allow 32 CPUs to share a bus without overloading it?
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我试图引导您找出答案......希望这会有所帮助。
需要多少个 CPU 才能使 400-MHZ 总线饱和？
计算处理器的数量是简单的除法。您知道总线速度是多少以及每个处理器的操作数。这几乎是显而易见的答案。
现在在使用缓存且缓存命中率为 90% 的系统中重复此问题。
好的，所以在这里您可以计算出每个处理器有多少条指令正在访问总线，并使用该数字而不是使用 200 MIPS 数字。与上面的划分相同。
最后，需要多少缓存命中率才能允许 32 个 CPU 共享总线而不使其过载？
这基本上与上述相反...您知道总线速率以及所需的总线数量处理器。计算出每个处理器（部门）有多少条指令到达总线，然后使用该数字来计算每个处理器的高速缓存命中率（也是部门）。
I am trying to guide you to figuring out the answers... hopefully this helps.
how many CPUs will it take to saturate a 400-MHZ bus?
Computing the number of processors is simple division. You know what the bus speed is and the number of operations per processor. This is pretty much the obvious answer.
Now repeat this problem for a system in which caching is used and the caches have a 90% hit rate.
OK, so here you would figure out how many of the instructions are hitting the bus for each processor , and use that figure instead of using the 200 MIPS number. Same division as above.
Finally, what cache hit rate would be needed to allow 32 CPUs to share a bus without overloading it?
This is basically the reverse of the above... you know that bus rate, and the desired nuumber of processors. Figure out how many instructions are reaching the bus for each processor (division), and then use that number to figure out each processor's cache hit ratio (also division).