VHDL ALU 未定义值
我正在学习 VHDL 来对 FPGA 进行编程,这是一些基本(但对我来说很难)的项目。我有这个ALU。它应该是一个 4 位 ALU。但是当我想要进行Add操作时,result
的值为UUUU
。对于所有其他操作都工作正常。
有什么建议吗?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port (
clk: in std_logic;
reset: in std_logic;
operation: in std_logic_vector (2 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal A : std_logic_vector (3 downto 0) := "0001";
signal B : std_logic_vector (3 downto 0) := "1111";
signal result : std_logic_vector (7 downto 0);
signal flags : std_logic_vector (2 downto 0); -- [S,OF,Z]
begin
process (operation) begin
flags <= (others => '0');
result <= (others => '0');
case operation is
when "000" =>
result <= std_logic_vector((unsigned("0000"&A) + unsigned(B)));
flags(1) <= result(4);
when "001" =>
if (A >= B) then
result <= std_logic_vector(unsigned("0000"&A) - unsigned(B));
flags(2) <= '0';
else
result <= std_logic_vector(unsigned("0000"&B) - unsigned(A));
flags(2) <= '1';
end if;
when "010" =>
result <= "0000"&A and "0000"&B;
when "011" =>
result <= "0000"&A or "0000"&B;
when "100" =>
result <= "0000"&A xor "0000"&B;
when "101" =>
result <= not ("1111"&A);
when "110" =>
result <= not ("1111"&B);
when "111" =>
result <= std_logic_vector(unsigned(A) * unsigned(B));
when others =>
result <= (others => 'Z');
end case;
end process;
end Behavioral;
I'm learning VHDL for programming a FPGA, basic (but hard-for-me) projects. I have this ALU. It is supossed to be a 4-bit ALU. But when I want to make the Add operation the value of result
is UUUU
. For all other operations is working fine.
Any advise?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port (
clk: in std_logic;
reset: in std_logic;
operation: in std_logic_vector (2 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal A : std_logic_vector (3 downto 0) := "0001";
signal B : std_logic_vector (3 downto 0) := "1111";
signal result : std_logic_vector (7 downto 0);
signal flags : std_logic_vector (2 downto 0); -- [S,OF,Z]
begin
process (operation) begin
flags <= (others => '0');
result <= (others => '0');
case operation is
when "000" =>
result <= std_logic_vector((unsigned("0000"&A) + unsigned(B)));
flags(1) <= result(4);
when "001" =>
if (A >= B) then
result <= std_logic_vector(unsigned("0000"&A) - unsigned(B));
flags(2) <= '0';
else
result <= std_logic_vector(unsigned("0000"&B) - unsigned(A));
flags(2) <= '1';
end if;
when "010" =>
result <= "0000"&A and "0000"&B;
when "011" =>
result <= "0000"&A or "0000"&B;
when "100" =>
result <= "0000"&A xor "0000"&B;
when "101" =>
result <= not ("1111"&A);
when "110" =>
result <= not ("1111"&B);
when "111" =>
result <= std_logic_vector(unsigned(A) * unsigned(B));
when others =>
result <= (others => 'Z');
end case;
end process;
end Behavioral;
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评论(2)
我可以看到所有
U
发生的唯一方法(代码按原样)是进程从不执行。这意味着您在添加操作的操作
信号上必须没有任何事务。这只会引发更多问题:
您是否确实得到了
U
(也许不是X
?):还有其他东西在驱动信号吗?你能发布你的测试平台代码吗?
The only way I can see all
U
s happening (with the code as is) is if the process never executes. Which means you must have no transactions on theoperation
signal for the add operation.Which only raises more questions:
Are you definitely getting
U
s (notX
s maybe?): is something else driving the signal as well?Can you post your testbench code?
查看代码时首先想到的两件事是:
您应该在进程敏感度列表中包含
A
和B
(现在它只包含操作
)。您不能使用
result(4)
来设置flags(1)
,因为result(4)
只会在之后更新该过程,并且结果
本身不再出现在敏感度列表中,因此不会再次触发该过程以反映更改的值。最好的选择可能是将总和存储在变量
中,然后将其分配给result
和溢出位。The first two things that come to mind looking at your code are:
You should include
A
andB
in the process sensitivity list (now it only containsoperation
).You can't use
result(4)
to setflags(1)
, asresult(4)
will only be updated after the process, andresult
itself isn't on the sensitivity list again so the process won't be triggered again to reflect the changed value. The best option is probably to store the sum in avariable
, then assign that toresult
and the overflow bit.