verilog中的组合硬件乘法
假设我有一个像这样的乘法器代码，
module multiply(
output [63:0] result,
input [31:0] a,
input [31:0] b
);
assign result = a * b;
endmodule
这会产生很多门。
应该使用什么更好的方法来实现组合乘法器？
Suppose I have a multiplier code like this,
module multiply(
output [63:0] result,
input [31:0] a,
input [31:0] b
);
assign result = a * b;
endmodule
This produces a lot of gates.
What preferable method should be used to implement combinatorial multiplier?
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硬件乘数很大，您只需要忍受它！
当输入位宽变大时，乘法器也会变大。因此，如果您的操作数之一不需要完整的 32 位，则将此大小减小到最小值将减小最终硬件的大小。
如果您乘以固定数字，我认为编译器也可以进行一些优化来限制硬件的大小。或者您可以对固定数字使用不同的编码方案，例如 CSD 这将减少加法器的数量在乘法器中，进一步减小其面积。
如果您需要大量乘法器并且拥有快速时钟，也许您可以重复使用单个硬件乘法器来进行许多计算。这意味着编写一些控制/流水线逻辑来安排乘法，并且您可能需要一些内存，但它可以节省您的总体空间。在这种情况下，您将设计一个迷你 DSP 数据路径。
Hardware multipliers are big, you just have to live with it!
Multipliers will get bigger as its input bit widths get bigger. So if you don't need the full 32 bits on one of you operands, then reducing this size to the minimum will reduce the size of the resulting hardware.
If you're multiplying by a fixed number, I think the compiler can make some optimizations to limit the size of the hardware too. Or you can use different encoding schemes for the fixed number such as CSD that will reduce the number of adders in the multiplier, further reducing its area.
If you need loads of multipliers and have a fast clock, maybe you can reuse a single hardware multiplier for many calculations. This means writing some control/pipelining logic to schedule your multiplies, and you might need some memory, but it can save you area overall. You'd be designing a mini-DSP datapath in this case.
如果您可以放弃组合要求，则可以使用加法器和累加器，如果速度不是一个大问题并且您能够在多个时钟上处理操作数。一些低功耗/低成本/小面积处理器的 ISA 中没有专用的乘法指令，或者乘法asm指令被前端指令解码器变为加法运算为加法微码运算。
如果您要使用此方法，则必须为数据握手，因为输入稳定后 1 个周期输出不再有效。
If you can forgo the combinatorial requirement, you can do multiplication using an adder and an accumulator, if speed isn't a large concern and you're able to process the operands over multiple clocks. Some low power/low cost/small area processors don't have dedicated multiply instructions in their ISA, or the multiply asm instruction is changed into addition operations by the front-end instruction decoder into addition microcode operations.
If you were to use this methodology, you'd have to create additional signals for the data hand-shake, since the output is no longer valid 1 cycle after the input settles.
由 verilog 乘法器生成的可能不是最佳的。在运动乘法器和加法器领域有很多研究。这是相当通用且良好的 add/mul 生成器之一：
http://www.aoki.ecei.tohoku.ac.jp /arith/mg/algorithm.html
此页面描述了许多 add/mul low-lewel 实现
Generated by verilog multiplier may be non-optimal. There is a lot of research in area of evvective multipliers and adders. And here is one of rather universal and good generator of add/mul:
http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html
This page has descriptions of many add/mul low-lewel implementations