D 触发器的最小数量
我遇到了以下问题，无法确定答案。您有任何建议吗？任何帮助将不胜感激。
斐波那契数列 F(n) 的定义为 F(1)=1、F(2)=1，并且对于所有整数 n>= 3，Fn=F(n-2) + F(n-1)。设计一个输出前七个斐波那契数（即 F1 到 F7 ）然后回绕的计数器电路所需的最少数量的 D 触发器（以及组合逻辑）？
(A) 3 (B) 4 (C) 5 (D) 6 (E) 7
提前致谢
I have encountered the following question and can't be sure on the answer. Do you have any suggestions, any help would be much appreciated.
The Fibonacci sequence F(n) is defined by F(1)=1, F(2)=1, and Fn=F(n-2) + F(n-1) for all integers n>= 3. What is the minimal number of D flip-flops required (along with combinational logic) to design a counter circuit that outputs the first seven Fibonacci numbers (i.e., F1 through F7 ) and then wraps around?
(A) 3 (B) 4 (C) 5 (D) 6 (E) 7
Thanks in advance
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获得七个不同输出所需的触发器最少数量仅为 3 个。但随后它涉及大量组合电路，用于将七个唯一输出解码为所需的斐波那契序列。其中一个解码电路使用四个 4:1 多路复用器，其中每个多路复用器输出代表斐波那契序列的一位。
但是使用 4 个触发器，我们可以获得一个同步计数器，它仅经历这些状态 1、1、2、3、5、8、13 并回绕。我认为这个过程涉及的电路要少一些。这里只需要注意区分 1 的出现两次，这可以通过使用额外的与非门来完成。
The minimum number of flipflops required would be only 3 for getting seven different outputs. But then it involves a lot of combinatorial circuitary for decoding the seven unique outputs into the required fibonacci sequence.One of those decoding circuit is using four 4:1 mux where, each mux output represents one bit of the fibonacci sequence.
But using 4 flipflops we can get a synchronous counter which goes through only these states 1,1,2,3,5,8,13 and wraping around. I think that this process involves a bit less circuitary.Here care should be taken only to differentiate the occurence of 1 twice, which, can be done through the use of an extra nand gate.
首先，您需要能够数到 7。这就是触发器的用武之地，因为它们具有您需要能够记住计数的内存。一种简单的方法是构造一个环形缓冲区，但由于允许无限的组合逻辑，因此您可以通过构造二进制计数器来改进这一点。
现在您已经拥有了一个提供 7 个独特输出的电路，您可以使用进一步的组合逻辑来增强该电路，将这些输出解码为您选择的 7 个值。
First, you need to be able to count to 7. This is where the flip-flops come in, because they have the memory that you need to be able to remember the count. A simple approach would be to construct a ring buffer, but since you're allowed infinite combinatorial logic you can improve on this by constructing a binary counter.
Now that you have a circuit that provides 7 unique outputs, you can then augment that with further combinatorial logic to decode those outputs into the 7 values of your choice.
您可以使用线性反馈移位寄存器：
总共需要 7 个触发器 (4+3)。
因为您的范围很小，所以您要添加的最大数字是 8 和 5，以获得 F(7)=13
现实世界的设计也会记录 F(n) 输出（出于时序原因）。
无需数到 7 本身 - 该系统可以自由运行，并且随着阶段宽度的增加，可以数到任意数量。如果您想要固定长度的序列，则需要一个触发值来重置自身。
You can use a linear feedback shift register:
You need 7 flops in total (4+3).
Because your range is small the biggest numbers you will add are 8 and 5 to get F(7)=13
A real world design would register the F(n) output too (for timing reasons).
There is no need to count to 7 itself - this system could free-run and with increased stage widths count as high as you like. It would need a trigger value to reset itself if you wanted a fixed length sequence.