直接向 x86-64 中的 TLB 提供物理地址
是否可以以长模式直接向 x86-64 架构上的 TLB 提供给定虚拟地址的物理地址？
例如，假设我在 PML4E 中放了 0，那么就会触发页错误异常，因为会发现无效地址，在异常期间 CPU 可以通过使用某些指令告诉 TLB 该虚拟地址位于 X 物理地址页框？
我想这样做是因为通过代码我可以轻松地知道物理地址在哪里，这样就可以避免昂贵的页面遍历。
Is it possible to provide physical address for a given virtual address in a direct way to the TLB on x86-64 architectures in long mode?
For example, lets say, I put zeros in PML4E, so a page fault exception will be triggered because an invalid address will be found, during the exception can the CPU tell the TLB by using some instruction that this virtual address is located at X physical page frame?
I want to do this because by code I can easily tell where the physical address would be, and this way avoid expensive page walk.
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不，您需要将页面放入 TLB。准确地说，您需要创建/更新适当的 PTE（如果需要，可以使用 PDE 和 PDPE）。围绕 MMU 管理的一切都以某种方式基于页表和 TLB。甚至用户/管理员保护模式也是作为映射页面的特殊标志来完成的。
为什么您认为“页面遍历”是昂贵的操作？它一点也不贵。要确定必须更新的 PTE，您只需要取消引用 4 个指针：PML4E -> PDPE->偏微分方程 ->英语口语考试。这些条目只是相关表中的索引。要获得 PML4E，您需要使用在页错误处理期间获取的 39-47 位地址，并将该值用作 PML4 表中的索引。要获得 PDPE，您需要 30-39 位地址作为 PDE 表中的索引等。它不会减慢您的系统速度。我认为分配物理页面需要更多时间。
No, you need to put a page to the TLB. To be precise, you need to create/update appropriate PTE (with PDE and PDPE if needed). Everything around MMU management is somehow based on page tables and TLB. Even user/supervisor protection mode is done as a special flag of mapped page.
Why do you think that "page walk" is expensive operation? It is not expensive at all. To determine the PTE that must be updated you need to dereference only 4 pointers: PML4E -> PDPE -> PDE -> PTE. These entries are just indices in related tables. To get PML4E you need to use 39-47 bits of address taken during page fault handling and use the value as an index in PML4 table. To get PDPE you need 30-39 bits of an address as an index in PDE table and so on. It's not the thing that can slow down your system. I think allocation of a physical page takes more time than that.