结果在 4 位 MIPS ALU 中以 VHDL 形式稳定？
考虑到第一个问题进展顺利，但仍然需要一点帮助，再次是练习考试，我已经有了答案，只需要推理和思考过程，谢谢大家。
考虑下一页所示的 4 位版本的 MIPS ALU。这里add/subt决定是进行加法(add/subt = 0)还是减法(add/subt = 1)，并且op选择多路复用器输出(假设顶部输入由op 000等选择)。假设
2 输入和、或、异或或 Nor 需要 2 个时钟周期才能稳定在其最终输出
4 输入或 4 输入需要 4 个时钟周期才能稳定在其最终输出
6 输入多路复用器需要 6 个时钟周期才能稳定在其最终输出最终输出
距离总和和进位输出最新到达输入的 8 个刻度 1 位全加器的最终输出稳定下来
对于下面所示的输入，结果输出何时稳定在其最终值（忽略零和溢出测试）？
add/subt = 0 outputs settle at ?
op = 000
A = 1111
B = 0001
Considering the first question went so well, still need a little help though, again its for a practice exam and I have the answers, just need the reasoning and thought process, Thanks guys.
Consider a 4-bit version of MIPS ALU shown on the next page. Here add/subt determines whether an addition (add/subt = 0) or subtraction (add/subt = 1) takes place and op selects the multiplexor output (assume that the top input is selected by an op of 000, etc.). Assume that it takes
2 ticks for a 2-input and, or, xor, nor to settle at its final output
4 ticks for a 4-input nor to settle at its final output
6 ticks for a 6-input multiplexor to settle at its final output
8 ticks from the latest arriving input for the sum and carry outputs
of a 1-bit full adder to settle at their final output
When do the result outputs settle at their final values for the inputs shown below (ignoring the test for zero and for overflow)?
add/subt = 0 outputs settle at ?
op = 000
A = 1111
B = 0001
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浏览图表并在每个元素收到信号时写下增量数字。
对于整个加法器
LSB 块
时间到 5（2 输入 AND、OR、XOR）的时间为 2 个刻度。加法器需要 8 个时钟周期才能进行传播，因此启动后总共 10 个时钟周期后其输出才准备好。多路复用器（现在所有输入均已更新）需要 6 个时钟周期来处理，这意味着 LSB 添加电路在第一次完全传播之前总共需要 16 个周期。
LSB + 1 块
第二个加法器需要来自第一个加法器的进位位，因此它需要等待 10 个时钟周期才能开始添加正确的值。它以 18 个总滴答数输出到多路复用器，并在 24 个总滴答数完成。
LSB + 2 块
第三个加法器需要来自第二个加法器的进位位，因此它需要等待 20 个时钟周期才能开始添加正确的值。它以 28 个总滴答数输出到多路复用器，并在 34 个总滴答数完成。
MSB 块
第三个加法器需要来自第三个加法器的进位位，因此它需要等待 30 个时钟周期才能开始添加正确的值。它以 38 个总滴答数输出到多路复用器，并在 44 个总滴答数完成。
设置位
不为正，这是做什么的，但其信号直到启动后 40 个时钟周期才会进入 LSB 块中的多路复用器。通过 LSB 块中的多路复用器需要 6 个时钟周期，因此 46 个时钟周期后，最终信号已完成从 LSB 块到 result0 的传播，并已进入 4 位，因此整个加法器稳定在 46 个时钟周期 最糟糕的情况
零测试带来最终滴答计数为 50
总共 44 个滴答时溢出已准备好
我们给出的数字提供了最坏的情况（需要所有块的所有进位位）。
Go through the diagram and write delta numbers for each element as it gets its signal.
For the whole adder
LSB block
time through 5 (2-input AND, OR, XOR) is 2 ticks. The adder needs 8 ticks to propegate so its output isn't ready until 10 total ticks after start. The mux (now with all inputs updated) takes 6 ticks to process meaning the LSB adding circuit takes 16 ticks total before propagating completely the first time.
LSB + 1 block
The second adder needs the carry bit from the first adder so it needs to wait 10 total ticks before it can start adding the correct values. It outputs at 18 total ticks into the mux which is completed at 24 total ticks.
LSB + 2 block
the third adder needs the carry bit from the second adder so it needs to wait 20 total ticks before it can start adding the correct values. It outputs at 28 total ticks into the mux which is completed at 34 total ticks.
MSB block
the third adder needs the carry bit from the third adder so it needs to wait 30 total ticks before it can start adding the correct values. It outputs at 38 total ticks into the mux which is completed at 44 total ticks.
set bit
not positive what this is for but its signal doesnt get into the mux in the LSB block until 40 ticks after start. Going through the mux in the LSB block takes 6 ticks therefore 46 ticks later the final signal has finished propagating from the LSB block to result0 and has entered the 4-bit nor so the entire adder settles at 46 ticks WORST CASE
The test for zero brings the final tick count to 50
The overflow is ready at 44 total ticks
The numbers we are given offer a worst case (all carry bits for all blocks are needed).