VHDL Compare 不能在硬件中工作，但可以在模拟中工作
大家好，我有以下 VHDL，它在硬件中没有实现预期的功能，但在模拟中确实有效。基本上我有一个计数器，根据我想要输出某些数据的计数，我实现了多路复用器，如下所示：
write_data <=
('1' & '0' & "1111" ) when (data_cnt_r < 1) else
('0' & '0' & "1111" ) when (data_cnt_r >= 1 and data_cnt_r < 2 ) else
('0' & '0' & "0000" ) when (data_cnt_r >= 2 and data_cnt_r < 3 ) else
('0' & '0' & data_reg ) when (data_cnt_r >= 3 and data_cnt_r < 1027 ) else
('0' & '1' & CRC16_o(63) & CRC16_o(47) & CRC16_o(31) & CRC16_o(15) ) when (data_cnt_r >= 1027 and data_cnt_r < 1043 ) else
('0' & '0' & "1111");
我遇到的问题是，当计数为 1043 时，我看到 CRC 输出，而不是最后看到“1111”代码中的行。在模拟中，它的工作原理正如我所期望的那样。有更好的方法来写这个吗？有什么想法为什么会出现差异吗？
*根据要求编辑更多详细信息：
我使用的
use IEEE.STD_LOGIC_UNSIGNED.ALL;
data_cnt 是一个免费运行的计数器，一切都是 std_logic_vector 或 std_logic
signal data_cnt_r : std_logic_vector(11 downto 0); -- 12 bit counter
write_data 进入 BUFIO，它也是一个标准逻辑向量
Hi guys I have the following VHDL which isn't doing what it suppose to in hardware but it does work in simulation. Basically I have a counter and depending on the count I want certain data to be output I implemented the mux as following:
write_data <=
('1' & '0' & "1111" ) when (data_cnt_r < 1) else
('0' & '0' & "1111" ) when (data_cnt_r >= 1 and data_cnt_r < 2 ) else
('0' & '0' & "0000" ) when (data_cnt_r >= 2 and data_cnt_r < 3 ) else
('0' & '0' & data_reg ) when (data_cnt_r >= 3 and data_cnt_r < 1027 ) else
('0' & '1' & CRC16_o(63) & CRC16_o(47) & CRC16_o(31) & CRC16_o(15) ) when (data_cnt_r >= 1027 and data_cnt_r < 1043 ) else
('0' & '0' & "1111");
The problem I am getting is that when the count is 1043 I see the CRC output instead of seeing "1111" for the last line in the code. In the simulation it works like I would expect. Is there a better way to write this? Any ideas why the discrepancy?
*EDIT More details as requested:
I'm using
use IEEE.STD_LOGIC_UNSIGNED.ALL;
data_cnt is a free runnig counter, everything is std_logic_vector or std_logic
signal data_cnt_r : std_logic_vector(11 downto 0); -- 12 bit counter
write_data goes to a BUFIO and it is also a standard logic vector
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评论（1）
你的其他转变附近发生了什么？ (1027, 3, 2, 1)
这是在进程块中还是异步？
data_cnt_r 是无符号的吗？ data_reg 和 CRC 值怎么样？我假设两个 std_logic_vectors？
我们需要更多的上下文，
您可以尝试显式添加一个转换，看看它是否有帮助：
如果这实际上是在时钟进程块中，您可能会在一个时钟周期后看到 write_data 中的 CRC 值，但您也会看到这个问题你的其他转换（它们都会更新 data_cnt_r 后面的一个周期）
如果它位于非时钟进程块中，你可能会遇到意外的逻辑错误
另外，这更容易阅读。
What is happening near your other transitions? (1027, 3, 2, 1)
is this in a process block or is it asynch?
is data_cnt_r an unsigned? What about data_reg and CRC values? I assume both std_logic_vectors?
We need a little more context
you could try explicitly adding a transition to see if it helps ala:
if this is actually in a clocked process block you might see the CRC values in write_data a clock cycle later but then you would also see this problem around your other transitions (they would all update a cycle behind data_cnt_r)
You might be getting unexpected logical errors if its in an unclocked process block
Also this is a little easier to read.