Verilog 最佳实践 - 递增变量
我绝不是 Verilog 专家，我想知道是否有人知道这些增加值的方法中哪一种更好。抱歉，如果这个问题太简单了。
方式 A：
在组合逻辑块中，可能在状态机中：
//some condition
count_next = count + 1;
然后在顺序块中的某个位置：
count <= count_next;
或者方式 B：
组合块：
//some condition
count_en = 1;
顺序块：
if (count_en == 1)
count <= count + 1;
我见过比较多的方式A。方式 B 的一个潜在好处是，如果您在状态机的许多位置递增相同的变量，则可能只使用一个加法器而不是多个加法器；或者这是假的？
哪种方法是首选，为什么？两者都有明显的缺点吗？
谢谢。
I'm by no means a Verilog expert, and I was wondering if someone knew which of these ways to increment a value was better. Sorry if this is too simple a question.
Way A:
In a combinational logic block, probably in a state machine:
//some condition
count_next = count + 1;
And then somewhere in a sequential block:
count <= count_next;
Or Way B:
Combinational block:
//some condition
count_en = 1;
Sequential block:
if (count_en == 1)
count <= count + 1;
I have seen Way A more often. One potential benefit of Way B is that if you are incrementing the same variable in many places in your state machine, perhaps it would use only one adder instead of many; or is that false?
Which method is preferred and why? Do either have a significant drawback?
Thank you.
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任何综合工具都会尝试自动资源共享。他们做得如何取决于所编写的工具和代码。以下文档描述了设计编译器的一些功能。请注意，在某些情况下，面积越小意味着时机越差。
这取决于。 Verilog（用于综合）是实现某些逻辑电路的一种方法，但规范没有具体说明这是如何完成的。方式 A 可能与 FPGA 上的方式 B 相同，但由于无条件顺序分配，方式 A 与 ASIC 上的低功耗设计不一致。使用复位网络几乎是 ASIC 的一项要求，但由于许多 FPGA 都是在已知状态下启动的，因此如果不使用复位网络，您可以节省大量资源。
Any synthesis tool will attempt automatic resource sharing. How well they do so depends on the tool and code written. Here is a document that describes some features of Design Compiler. Notice that in some cases, less area means worse timing.
It depends. Verilog(for synthesis) is a means to implement some logic circuit but the spec does not specify exactly how this is done. Way A may be the same as Way B on an FPGA but Way A is not consistent with low power design on an ASIC due to the unconditional sequential assignment. Using reset nets is almost a requirement on an ASIC but since many FPGAs start in a known state, you can save quite a bit of resources by not having them.
我在 Verilog 代码中使用方式 A。我的连续块几乎没有逻辑；他们只是根据组合always块中计算的“wire regs”的值来分配寄存器。这样出错的机会就更少了。对于 Verilog，我们需要我们能得到的所有帮助。
I use Way A in my Verilog code. My sequential blocks have almost no logic in them; they just assign registers based on the values of the "wire regs" computed in the combinational always blocks. There is just less to go wrong this way. And with Verilog we need all the help we can get.
你对“更好”的定义是什么？
它可以是更好的性能（更快的合成电路最大频率）、更小的面积（更少的逻辑门）或更快的模拟执行。
让我们考虑 Xilinx 和 Altera FPGA 的较小面积情况。这些 FPGA 系列中的寄存器具有启用输入。在“方式 B”中，*count_en* 将直接映射到启用寄存器输入，这将导致逻辑门减少。本质上，“方式 B”为综合工具提供了更多“提示”，以帮助综合工具更好地综合该电路。此外，大多数 FPGA 综合工具（我指的是 Xilinx XST、Altera MAP、Mentor Precision 和 Synopsys Synplify）也可能会正确推断来自“A 路”的寄存器启用输入。
如果*count_en*被合成为启用寄存器输入，这将导致电路性能更好，因为您的计数器增量逻辑将具有更少的逻辑级别。
谢谢
What is your definition of "better" ?
It can be better performance (faster maximum frequency of the synthesized circuit), smaller area (less logic gates), or faster simulation execution.
Let's consider smaller area case for Xilinx and Altera FPGAs. Registers in those FPGA families have enable input. In your "Way B", *count_en* will be directly mapped into that enable register input, which will result in less logic gates. Essentially, "Way B" provides more "hints" to a synthesis tool how to better synthesize that circuit. Also it's possible that most FPGA synthesis tools (I'm talking about Xilinx XST, Altera MAP, Mentor Precision, and Synopsys Synplify) will correctly infer register enable input from the "Way A".
If *count_en* is synthesized as enable register input, that will result in better performance of the circuit, because your counter increment logic will have less logic levels.
Thanks