Xilinx ISE 构建时间和已编译的模块
有没有办法加快 Xilinx ISE 构建过程？我的项目中有多个 verilog HDL 文件。有时我会在一个文件的某个位置进行微小的更改。然而，构建时间与整个项目被更改时相同。我认为软件对于已经构建的模块没有任何优势。
我知道它的硬件，但是有什么办法吗？我真的为自己进步缓慢而烦恼。任何其他完成该过程的提示将不胜感激。
您真诚的
阿布巴卡
Is there a way to speed up Xilinx ISE build process? I have multiple verilog HDL files in my project. Sometimes I implement a minor change in at a place in one file. However the build time is same as if the whole project were changed. I think software does not offer any advantage for already build modules.
I know its hardware, but is there some way out. I am really trouble with my slow progress. Any other tips to make the process will be appreciated.
Yours Truely
Abu Bakar
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您可以采取很多措施来加速 FPGA 构建。其中：
- 平面规划
- 设计分区（Xilinx和Altera有一些差异）
- 添加错误路径和多周期路径约束
- 尝试综合和物理实现工具选项
- 重置方案的选择也会影响构建时间
- 不要过度限制时间，
我在书中更详细地讨论了这个主题。
谢谢。
There are quite a few things you can do to speed up an FPGA build. Among them:
- floorplanning
- design partitioning (Xilinx and Altera have some differences)
- adding false paths and mulitcycle paths constraints
- playing with synthesis and physical implementation tool options
- choice of the reset scheme can also affect the build time
- not over-constraining timing
I discuss this very topic in more detail in my book.
Thanks.
您可以对设计进行分区，以帮助加快大型设计中的布局和布线过程。但说实话，FPGA 构建总是相当漫长:(
这就是为什么我们大多数人开始在工作台上进行构建和调试，然后非常快速转移到在模拟器中调试代码（这编译速度非常快 - 秒），并且只有当它在那里工作时才能进行硅片的漫长构建（数小时）。
You can partition the design to help speed up the place and route process in a large design. But to be honest, FPGA builds are always going to be pretty lengthy :(
That's why most of us start out doing builds and debugging on the bench and very quickly move to debugging the code in a simulator (which is very fast to compile - seconds), and only when it works there doing the loooong build for silicon (hours).