处理器是否从“L1 代码”切换数据？到“L1 数据”缓存？
我想知道，微处理器（假设在长模式下的 SandyBridge 架构上）如何将数据从“L1 代码”缓存切换到“L1 数据”缓存，反之亦然？ 假设一个页面用于数据存储，因此它缓存在 L1 缓存中。然后，在操作系统执行期间，指令指针跳转（发出JMP指令）到当前缓存在L1数据缓存中的内存位置。处理器是否将数据从 L1 数据迁移到 L1 代码缓存？当数据管理指令在存储在 L1 代码缓存中的地址上发出时同样的问题（即意味着该地址适合数据存储，而不是代码执行） 处理器如何处理这些问题？
我问这个问题是因为我正在研究自修改代码，如果您有任何其他信息可以让我阅读有关代码缓存的详细信息，请发布链接/参考。
I would like to know, how does the microprocessor (lets say on SandyBridge architecture in long mode) switches data from 'L1 code' to 'L1 data' cache and vice versa ?
Lets say a page was used for data storage, so it is cached in L1 cache. Then , during the execution of the OS, the instruction pointer jumps (issuing a JMP instruction) to the memory location that is currently cached in L1 data cache. Does the processor migrates data from L1 data to L1 code cache? Same question for when the data management instruction is issued on an address that is stored in L1 code cache (i.e. meaning that the address became good for data storage, not code execution)
How does the processor handles these issues?
I am asking this because I am studying about self modifying code, if you have any additional info where I could read details about code cache, please post the link/reference.
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请参阅最新的 英特尔程序员手册，第 3 卷，系统编程，特别是这些部分：
我认为您不想了解并依赖于特定 CPU 型号的行为，因为这会使您的代码在不同或较新的 CPU 上不稳定。只需遵循有关如何设计和执行自我修改和交叉修改代码的官方指南即可。
而且您不想在运行时进行大量代码修改，因为缓存失效会导致相关的性能损失。
See the latest intel programmer's manual, vol 3, system programming, specifically these sections:
I don't think you want to know and become reliant on the behavior of specific CPU models, because it will make your code unstable on different or newer CPUs. Just follow the official guidelines on how to design and execute self and cross-modifying code.
And you don't want to do a lot of code modification at run time because of the associated performance penalties due to cache invalidation.