Verilog编译器错误
module router (clock, ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3, PacketIn0, PacketIn1, PacketIn2, PacketIn3, PacketOut0, PacketOut1, PacketOut2, PacketOut3);
input clock;
input ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3;
input [7:0] PacketIn0, PacketIn1, PacketIn2, PacketIn3;
output [7:0] PacketOut0,PacketOut1, PacketOut2, PacketOut3;
reg [3:0] bvp, vp;
reg [1:0] counter0, counter1, counter2, counter3;
reg [2:0] sel0, sel1, sel2, sel3;
reg [3:0] zero=0;
reg [7:0] addr0, addr1, addr2, addr3, out0, out1, out2, out3l;
wire np0, np1, np2, np3;
wire [7:0] PacketOut0, PacketOut1, Packetout2, Packetout3;
always@(posedge clock)
bvp[0]<=ValidPacket0;
if (ValidPacket0 && !bvp[0]) vp[0]=1'b1;
else vp[0]=0;
上面的代码给了我以下错误：
** Error: proj1a.v(23): near "[": syntax error, unexpected '[', expecting "IDENTIFIER" or "TYPE_IDENTIFIER" or '#' or '('
Line 23 is at the if statement.
有见解吗？
module router (clock, ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3, PacketIn0, PacketIn1, PacketIn2, PacketIn3, PacketOut0, PacketOut1, PacketOut2, PacketOut3);
input clock;
input ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3;
input [7:0] PacketIn0, PacketIn1, PacketIn2, PacketIn3;
output [7:0] PacketOut0,PacketOut1, PacketOut2, PacketOut3;
reg [3:0] bvp, vp;
reg [1:0] counter0, counter1, counter2, counter3;
reg [2:0] sel0, sel1, sel2, sel3;
reg [3:0] zero=0;
reg [7:0] addr0, addr1, addr2, addr3, out0, out1, out2, out3l;
wire np0, np1, np2, np3;
wire [7:0] PacketOut0, PacketOut1, Packetout2, Packetout3;
always@(posedge clock)
bvp[0]<=ValidPacket0;
if (ValidPacket0 && !bvp[0]) vp[0]=1'b1;
else vp[0]=0;
The above code gives me the following error:
** Error: proj1a.v(23): near "[": syntax error, unexpected '[', expecting "IDENTIFIER" or "TYPE_IDENTIFIER" or '#' or '('
Line 23 is at the if statement.
Any Insight?
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根据您想要执行的操作，您需要在
always @(posedge)之后的语句周围添加begin和end关键字 (并修复您的分配类型，请参阅如何解释 Verilog 中的阻塞与非阻塞分配？），或者您需要添加总是@(*)之前if/else 引入组合逻辑。Depending on what you're trying to do, you either need to add
beginandendkeywords around the statements afteralways @(posedge)(and fix your assignment type, see How to interpret blocking vs non blocking assignments in Verilog?), or you need to addalways @(*)before the if/else to introduce combinational logic.这个“if”块表示生成块，因为它出现在模块级别。代码
vp[0]=1'b1;是一个过程语句，仅允许在过程块内使用。编译器抱怨是因为它需要一个模块或 udp 实例，而该实例永远不会是后跟“[”的标识符。This 'if' block indicates a generate block because it appears at the module level. The code
vp[0]=1'b1;is a procedural statement which is only allowed inside a procedural block. The compiler is complaining because it is expecting a module or udp instance which would never be an identifier followed by a '['.