x86 设置脏页位时如何提示？
从软件的角度来看，弄脏内存页面的指令与内核实际在页表条目 (PTE) 中将该页面标记为脏页面之间的延迟是多少？
换句话说，如果一条指令弄脏了一页，下一条指令是否可以读取 PTE 并看到脏位设置？
我不关心实际经过的周期，仅当存在一个尚未设置脏位的软件可见窗口时。我似乎在参考手册中找不到任何保证。
From a software point of view, what is the latency between an instruction that dirties a memory page and when the core actually marks the page dirty in the Page Table Entry (PTE)?
In other words, if an instruction dirties a page, can the very next instruction read the PTE and see the dirty bit set?
I don't care about the actual elapsed cycles, only if there is a software visible window in which the dirty bit is not yet set. I can't seem to find any guarantees in the reference manuals.
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（3）
来自 AMD 手册（大约 2005 年），第 2 卷：系统编程：
Intel 的同上（大约 2006 年），第 3-A 卷：系统编程指南，第 1 部分：
更新：
来自最新的英特尔手册（第 3A 卷，系统编程指南）：
从第 8.1 节和第 8.2 节中的其余文本可以看出，一旦 CPU 使用锁定操作设置了脏位，其他 CPU 就应该开始看到更新后的值。
当然，您可能会遇到竞争条件，因为您首先在一个 CPU（或其一个线程）上将脏位读取为 0，然后另一个 CPU（或同一 CPU 上的另一个线程）导致该位设置为1，但这并不奇怪。
From the AMD's manual (circa 2005), Volume 2: System Programming:
Ditto from Intel (circa 2006), Volume 3-A: System Programming Guide, Part 1:
UPDATE:
From the latest Intel manual (vol 3A, System Programming Guide):
From the rest of the text in sections 8.1 and 8.2 it follows that once the CPU sets the dirty bit using the locked operation, the other CPUs should start seeing the updated value.
Of course, you may have a race condition in that you first read the dirty bit as 0 on one CPU (or in one of its threads) and later another CPU (or another thread on the same CPU) causes this bit to be set to 1, but that isn't any unusual.
AMD64 架构程序员手册第 2 卷：系统编程（修订版 3.22，2012 年 9 月）
（强调我的。）
AMD64 Architecture Programmer’s Manual Volume 2: System Programming (revision 3.22, Sept. 2012)
(Emphasis mine.)
根据 此文档，Intel x86缓存有关页表的信息。文中指出，如果脏位被软件清除，则CPU仍有可能将其视为等于1。
现在，对于问题：如果CPU缓存了脏位，则有可能对PTE进行更新（页表项）不会立即发生。它可能会被缓存写回策略延迟。
同一文档的第 1651 页描述了刷新内部高速缓存的 WBINVD 指令。它并没有说这包括CPU缓存的所有数据。
According to page 2033 of this document, Intel x86 caches information about the page table. The text states that if the dirty bit is cleaned by software, there's a possibility that the CPU still sees it as equal to 1.
Now, for the question: if the CPU caches the dirty bit, there's a possibility that the update to the PTE (page-table-entry) does not take place immediately. It could be delayed by a cache-write-back policy.
Page 1651 of the same document describes the WBINVD instruction, that flushes internal caches. It does not say that this includes all data cached by the CPU.