x86 cr3 和 linux swqpper_pg_dir
在 Linux 源代码（版本 2.6.18）中：
movl $swapper_pg_dir-__PAGE_OFFSET,%eax
movl %eax,%cr3
movl %cr0,%eax
orl $0x80000000,%eax
movl %eax,%cr0 /* ..and set paging (PG) bit */
ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */
还有 load_cr3(pgdir) 和 write_cr3(x) 宏：
#define load_cr3(pgdir) write_cr3(__pa(pgdir))
#define write_cr3(x) \
__asm__ __volatile__("movl %0,%%cr3": :"r" (x))
看起来整个 cr3< /code> 控制寄存器存储页目录的地址。然而，当我引用 intel ia-32 Developer's_Manual 时，它讲述了一个不同的故事。以下是intel手册上的内容：
name 0.............11 12.................31
cr3 flags address of page directory
PDE flags address of page table
PTE flags address of 4kb page frame
手册上说cr3的20个最高有效位存储的是页目录的地址，而不是整个cr3寄存器的地址。这也是合理的，因为页目录正好是 4kb，因此地址的 12 个最低有效位始终为零。
是不是有点奇怪？ Linux代码只是将页目录的地址分配给cr3，而不是swapper_pg_dir的20个最高有效位。 cr3 寄存器到底存储什么，英特尔手册建议的地址或格式？
以下链接是英特尔手册： http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
In Linux source code (version 2.6.18):
movl $swapper_pg_dir-__PAGE_OFFSET,%eax
movl %eax,%cr3
movl %cr0,%eax
orl $0x80000000,%eax
movl %eax,%cr0 /* ..and set paging (PG) bit */
ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */
And also the load_cr3(pgdir) and write_cr3(x) macros:
#define load_cr3(pgdir) write_cr3(__pa(pgdir))
#define write_cr3(x) \
__asm__ __volatile__("movl %0,%%cr3": :"r" (x))
It seems like that the whole cr3 control register stores the address of Page Directory. However, when I reference the intel ia-32 Developer's_Manual it tells a different story. The following is what the intel manual says:
name 0.............11 12.................31
cr3 flags address of page directory
PDE flags address of page table
PTE flags address of 4kb page frame
The manual says that the 20 most significant bits of cr3 stores the address of the page directory instead of the whole cr3 register. It is also reasonable since the page directory is exactly 4kb, so the 12 least significant bits of the address is always zero.
Isn't it a little bit strange? The linux code just assigns the address of the page directory to the cr3 instead of the 20 most significant bits of the swapper_pg_dir. What exactly does the cr3 register stores, the address or the format that intel manual suggests?
The following link is the intel manual: http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
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对于32位分页，页目录的地址必须是4096的倍数，即其12 LSB为零。但是，设置 cr3 的操作码加载 32 位，而不是 20 位。加载 cr3 时，其高 20 位用于页目录地址，低 12 位被解释为可能影响较新处理器版本中的分页行为的标志。这些标志的“安全”设置为零，这正是 Linux 所做的：它用 32 位值加载 cr3，而该值的 12 LSB 恰好等于 0（因为该 32 位值已被视为内存）地址是 4096 的倍数）。
For 32-bit paging, it is mandatory that the address of the page directory is a multiple of 4096, i.e. its 12 LSB are zero. However, the opcode for setting cr3 loads 32 bits, not 20 bits. When cr3 is loaded, its 20 upper bits are used for the page directory address, and the lower 12 bits are interpreted as flags which may affect paging behaviour in newer processor versions. The "safe" setting for these flags is zero, and that's precisely what Linux does: it loads cr3 with a 32-bit value which happens to have its 12 LSB equal to zero (because that 32-bit value has been taken as a memory address which is a multiple of 4096).
如果
swapper_pg_dir-__PAGE_OFFSET是 4096 的倍数，那就没什么奇怪的了。CR3LSB 中的零是有效的：
There's nothing strange if
swapper_pg_dir-__PAGE_OFFSETis a multiple of 4096.Zeroes in CR3 LSBs are valid: