The data outputs go high impedance to allow other chips to use the data bus -- any operations that occur on the bus are ignored. When it gets a low signal on the CS pin, it will process any bus transactions it sees according to its data sheet. It will then latch the data from the data bus or drive data onto the data bus for a read or write cycle respectively.
The usual hardware design is the CS pin is driven by the output of the address decoder. When the address is seen to be in range for the target device, the address decoder drives that device's chip select pin active. That way, only the target device responds to each bus operation.
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数据输出变为高阻抗，以允许其他芯片使用数据总线——总线上发生的任何操作都将被忽略。当它在 CS 引脚上收到低信号时，它将根据其数据表处理它看到的任何总线事务。然后，它将锁存来自数据总线的数据或将数据驱动到数据总线上，分别用于读或写周期。
通常的硬件设计是CS引脚由地址译码器的输出驱动。当地址被视为在目标设备的范围内时，地址解码器会驱动该设备的片选引脚处于活动状态。这样，只有目标设备响应每个总线操作。
The data outputs go high impedance to allow other chips to use the data bus -- any operations that occur on the bus are ignored. When it gets a low signal on the CS pin, it will process any bus transactions it sees according to its data sheet. It will then latch the data from the data bus or drive data onto the data bus for a read or write cycle respectively.
The usual hardware design is the CS pin is driven by the output of the address decoder. When the address is seen to be in range for the target device, the address decoder drives that device's chip select pin active. That way, only the target device responds to each bus operation.