如何思考数字电路设计

发布于 2024-12-10 06:11:40 字数 460 浏览 0 评论 0原文

如何以抽象的方式思考设计数字逻辑芯片?

我目前正在学习“计算系统的要素”,我正在阅读第一章,并且我已经从 Nand 开始实现了以下门。

Not

And

Or

Xor

Mux

DMux

16bit Not

16bit And

16bit Or

16bit Mux

8 way 或者

我现在一直在尝试实现 16 位四路 Mux。

我尝试将真值表转换为规范符号,但最终陷入了混乱。使用规范表示对于“较小”的芯片效果很好,但现在非常复杂。我怎样才能考虑以一种不只是将随机芯片混在一起的方式来组装一个“复杂”的芯片?

编辑:

我对四路复用器的 16 位部分并不感到困惑。我计划在阵列中使用一堆四路复用器。 4路多路复用器是我所坚持的部分。

How does one go about thinking about designing digital logic chips in an abstract way?

I'm currently working through "The Elements of Computing Systems" I'm in the first chapter, and I've implemented the following gates, starting from Nand.

Not

And

Or

Xor

Mux

DMux

16bit Not

16bit And

16bit Or

16bit Mux

8 way Or

I'm now stuck trying to implement a 16 bit four way Mux.

I've tried converting the truth table into canonical notation, but I end up with a gigantic mess. Using canonical representation worked well for "smaller" chips, but is now immensely complicated. How can I think about putting together a "complicated" chip in a way that doesn't involve just mashing together random chips?

Edit:

I'm not really confused about the 16 bit part of the four way Mux. I planned on just using a bunch of four way Muxes in an array. The 4 way mux is the part I'm stuck on.

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深居我梦 2024-12-17 06:11:40

让我们从两个输入多路复用器开始。

两个输入 A 和B 和选择线 S。当 A 或 B 为“1”并且选择线选择该输入时,输出将为“1”,否则为“0”。因此,要么:

A=1 and S=0
B=1 and S=1

将其写为门:

(A and (not S)) or (B and S)

将其扩展到 4 路(S 现在是 2 位):

A = 1 and S=0
B = 1 and S=1
C = 1 and S=2
D = 1 and S=3

(A and (not S1) and (not S0)) or
(B and (not S1) and (    S0)) or
(C and (    S1) and (not S0)) or
(D and (    S1) and (    S0))

我们可以看到一种正在出现的模式,即每个输入都与一些“启用项”进行“与”操作,该“启用项”会打开该输入或关闭。由于启用项是排他性的(任何时候只有一项可以为真),因此效果是将输出切换到所需的输入。

这可以扩展到任意大小的 MUX。

Lets start with a two input mux.

Two inputs A & B and a select line S. The output will be '1' when the A or B is '1' and the select line selects that input, else it's '0'. So either:

A=1 and S=0
B=1 and S=1

Writing that out as gates:

(A and (not S)) or (B and S)

Expand that up to a 4 way (S is now 2 bits):

A = 1 and S=0
B = 1 and S=1
C = 1 and S=2
D = 1 and S=3

(A and (not S1) and (not S0)) or
(B and (not S1) and (    S0)) or
(C and (    S1) and (not S0)) or
(D and (    S1) and (    S0))

We can see a pattern emerging which is that every input is AND'ed with some "enabling term" which switches that input on or off. As the enabling terms are exclusive (only one can be true at any time) the effect is to switch the output to the desired input.

This can be extended up to any size of MUX.

甜嗑 2024-12-17 06:11:40

我赞赏你的“从底层开始,逐步提高”的方法,它将帮助你理解随着时间的推移越来越复杂的电路所涉及的内容。

还值得指出的是,一旦您开始大规模地设计数字逻辑芯片,现在通常会在更高的水平上完成。通常使用硬件描述语言(通常是 Verilog 或 VHDL),甚至在某些领域使用 C 来表示芯片的某些部分。

一旦达到该级别,您就很少编写 MUX 代码,但是在编写文本描述时知道您正在要求综合工具为您生成一个 MUX 代码,并且您已经掌握了一些内容,这是非常有用的它可能有多大(以门为单位)。

另一点需要注意的是,如果您转向使用 FPGA 进行设计,您的基本构建块不是 NAND 门,而是 4 或 6 个输入查找表(以及各种其他辅助块)。这会改变您的观点,因为 4(或 6)个输入的任何函数的成本都是相同的......

I applaud your "start at the bottom and work up" approach, it will help you appreciate what is involved in more and more complex circuits over time.

It might also be worth pointing out that once you come to designing digital logic chips on a larger scale, it's usually done at a much higher level these days. Often using a Hardware Description Language (usually Verilog or VHDL), or even using C for parts of the chip in some domains.

Once you work at that level, you very rarely write the code for a MUX, but it is very useful to know as you write the textual description that you're asking the synthesis tool to produce one for you, and that you have some grasp of how "big" (in gates) it's likely to be.

Another point to note is that if you move to designing with FPGAs, your fundamental building block is not NAND gates, but 4 or 6 input look-up tables (with sundry other assisting blocks). That changes your viewpoint, as any function of 4 (or 6) inputs costs the same...

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