B指令编码
在学校，我正在编写一个 ARM 模拟器。在 ARM ARM (http://www .eecs.umich.edu/~prabal/teaching/eecs373-f11/readings/ARMv7-M_ARM.pdf）计算第二个和分支偏移量的第三高位为 I1 = NOT(J1 EOR S); 和 I2 = NOT(J2 EOR S);（ARM ARM 第 239 页）。有谁知道为什么会这样？由于某种原因，它似乎导致了我的错误。
For school I'm working on writing an ARM simulator. In the ARM ARM (http://www.eecs.umich.edu/~prabal/teaching/eecs373-f11/readings/ARMv7-M_ARM.pdf) the calculate the second and third highest bit for the branch offset as I1 = NOT(J1 EOR S); and I2 = NOT(J2 EOR S); (ARM ARM pg 239). Does anyone know why it's this way? For some reason it seems to be causing me errors.
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这有点令人困惑，但它似乎是一种将 I1 和 I2 位映射到有效指令编码的技术。
Thumb 分支指令被编码为一对 16 位子指令。每个 16 位子指令都需要其自己独特的指令编码。
“S”位是符号位，因此我们可以看到，无法从第一个 16 位子指令中区分 Encoding T3 和 Encoding T4。
在第二个子指令中，位 12 区分编码 T3 和 T4。然而，直接使用 I1 和 I2 会与现有指令发生冲突，因此它们被分成四种编码之一，每种编码决定分支的范围。
It's a bit of a puzzler but it appears to be a technique to map the I1 and I2 bits into valid instruction encodings.
Thumb branch instructions are encoded as a pair of 16-bit sub-instructions. Each 16-bit sub-instruction needs its own distinct instruction encoding.
The 'S' bit is a sign bit so we can see there's no way to distinguish Encoding T3 and Encoding T4 from the first 16-bit sub-instruction.
In the second sub-instruction bit 12 distinguishes Encoding T3 and T4. However, using I1 and I2 directly would clash with existing instructions so they're munged into one of four encodings, each determining the range of the branch.