在 Verilog 中编码 RAM 的更好方法
哪种代码写RAM比较好？
在
always块内分配data_out：模块内存( 输出寄存器[7:0] data_out， 输入[7:0]地址， 输入[7:0]数据输入， 输入写启用， 输入时钟 ）； reg [7:0] 内存 [0:255]; 总是@(posege clk)开始 if (write_enable) 开始 内存[地址] <= data_in; 结尾 data_out <= 内存[地址]; 结尾 终端模块使用
assign语句分配data_out：模块内存( 输出[7:0]数据输出， 输入[7:0]地址， 输入[7:0]数据输入， 输入写启用， 输入时钟 ）； reg [7:0] 内存 [0:255]; 总是@(posege clk)开始 if (write_enable) 开始 内存[地址] <= data_in; 结尾 结尾 分配 data_out = 内存[地址]； 终端模块
有什么建议吗？
Which code is better in writing a RAM?
assigning
data_outinsidealwaysblock:module memory( output reg [7:0] data_out, input [7:0] address, input [7:0] data_in, input write_enable, input clk ); reg [7:0] memory [0:255]; always @(posedge clk) begin if (write_enable) begin memory[address] <= data_in; end data_out <= memory[address]; end endmoduleassigning
data_outusingassignstatement:module memory( output [7:0] data_out, input [7:0] address, input [7:0] data_in, input write_enable, input clk ); reg [7:0] memory [0:255]; always @(posedge clk) begin if (write_enable) begin memory[address] <= data_in; end end assign data_out = memory[address]; endmodule
Any recommendations?
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添加到工具的答案 - 如果您使用异步读取方法（情况2），它不会映射到FPGA中的RAM块，因为我知道的所有主要架构中的RAM块都具有同步读取。
to add to toolic's answer - if you use the asynchronous read method (case 2), it won't map to a RAM block in an FPGA, as the RAM blocks in all the major architectures I'm aware of have a synchronous read.
两种形式都有效，具体取决于您想要的管道类型。我始终建议遵循 Xilinx RAM 编码指南——这是确保代码合成正确的 FGPA 结构的好方法。
例如，您的示例 1 将合成为 Xilinx BRAM（即专用 Block Ram），因为它是同步读取，而您的示例 2 将合成为 Xilinx 分布式 RAM（因为它是异步读取）。
请参阅 Xilinx 文档 UG901（Vivado Design Suite 用户指南）中 RAM HDL 编码技术部分中的编码指南。它还很好地描述了 RAM 的同步读取和异步读取之间的差异。
Both forms are valid, depending on the type of pipelining you want. I always recommend following the Xilinx RAM coding guidelines -- it's a good way to ensure that the code synthesizes into proper FGPA constructs.
For example, your example 1 would synthesize into into Xilinx BRAM (i.e., dedicated Block Ram), since it is synchronous read, and your example 2 would synthesize into Xilinx Distributed Ram (since it is asynchronous read).
See the coding guidelines in Xilinx document UG901 (Vivado Design Suite User Guide), in the RAM HDL Coding Techniques section. It also has a good description of the difference between synchronous read and asynchronous read for RAMs.
在第二个程序中，会出现编译错误，因为我们无法为“Reg”“分配”值。
它会给出一个错误：“连续赋值的左侧寄存器非法”
In the second program, there would be compilation error as we can not 'Assign' a value to 'Reg'.
It will give an error saying: 'Register is illegal in left-hand side of continuous assignment'
这取决于您的要求。
这会记录您的内存输出。如果您将其综合到门，您将比情况 2 多 8 个触发器。这意味着您使用更多的面积。这也意味着您的输出相对于时钟的传播延迟将比情况 2 更小。此外，输出数据直到下一个时钟周期才可用。
您的输出数据将在写入时的同一时钟周期内可用，尽管相对于时钟的传播延迟更长。
您需要根据您的要求决定使用哪个。
第三种选择是使用生成的 RAM，它是一个硬宏。与情况 1 和 2 相比，这应该具有面积、功率和可能的时间优势。
It depends on your requirements.
This registers your memory output. If you are synthesizing this to gates, you will have 8 more flip-flops than in case 2. That means you use a little more area. It also means your output will have less propagation delay relative to the clock than case 2. Furthermore, the output data will not be available until the next clock cycle.
Your output data will be available within the same clock cycle as it was written, albeit with longer propagation delay relative to the clock.
You need to decide which to use based on your requirements.
A third option is to use a generated RAM, which is a hard macro. This should have area, power and possibly timing advantages over both case 1 and 2.