在 Verilog 中转换线值以进行进一步处理
我是 Verilog 新手。
我已经编写了将线值转换为整数的代码:
wire [31:0] w1;
integer k;
always @ (w1) k = w1;
现在,对于下一部分,我收到错误!
wire [63:0] w2; // Suppose it contains some value
wire [63:0] w3;
assign w3[k-1:0] = w2[k-1:0]; // ERROR in this line
ERROR : k is not a constant.
我该如何解决这个问题?
I'm new to Verilog.
I have written code to convert a wire value to an integer:
wire [31:0] w1;
integer k;
always @ (w1) k = w1;
Source: converting a wire value to an integer in verilog
Now, for the next part I get an ERROR!
wire [63:0] w2; // Suppose it contains some value
wire [63:0] w3;
assign w3[k-1:0] = w2[k-1:0]; // ERROR in this line
ERROR : k is not a constant.
How do I solve this issue?
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Verilog 要求部分选择(例如
[msb:lsb]
的代码用于选择向量的一部分)是恒定的。要访问可变大小的位组需要更复杂的东西。这是一种实现方法:这里的技术是构造一个由 64 个 0 后跟 64 个 1 组成的向量,将该向量移位一个可变量,然后使用该向量的一部分作为限定掩码来控制传输哪些位从
src
到dest
。一个相关的概念对您的示例没有帮助,但值得注意:Verilog-2001 引入了“索引部分选择”。索引部分选择指定基本索引和宽度。宽度需要恒定,但基本索引不需要恒定。索引部分选择的语法为
vec[base+:width]
或vec[base-:width]
。Verilog requires that part selects (code like
[msb:lsb]
to select part of a vector) be constant. To access a variable-sized group of bits requires something more complicated. Here is one way to do it:The technique here is to construct a vector of 64 zeros followed by 64 ones, shift that vector by a variable amount, and then use a portion of the vector as a qualifying mask to control which bits are transferred from
src
todest
.A related concept which does not help in your example but which is worth being aware of: Verilog-2001 introduced the "indexed part-select". An indexed part select specifies a base index and a width. The width is required to be constant but the base index does not need to be constant. The syntax for an indexed part select is
vec[base+:width]
orvec[base-:width]
.Verilog 2001 中的部分选择运算符可能对您想要实现的目标很有用。
基本上,verilog 允许起始索引是可变的,但需要赋值的宽度是恒定的。 “+:”运算符表示从索引值向上计数,“-:”运算符表示从索引值向上计数。
你可以做类似的事情,
赋值 w3[k-1 -: 8 ] = w2[k-1 -: 8]; // 其中向下复制8位
在下面的文档中搜索“+:”。
http://www.sutherland-hdl.com/papers/2001 -Wescon-tutorial_using_Verilog-2001_part1.pdf
注意,通常可变部分选择被认为是不好的verilog。
The part select operators in Verilog 2001 could be useful for what you want to achieve.
Basically verilog allows for the starting index to be variable but needs the width of the assignment to be constant. The "+:" operator indicates counting upwards from the index value and vice-versa for "-:".
You can do something like,
assign w3[k-1 -: 8 ] = w2[k-1 -: 8]; // Where 8 bits is copied downwards
Search for "+:" in the below document.
http://www.sutherland-hdl.com/papers/2001-Wescon-tutorial_using_Verilog-2001_part1.pdf
Word of caution, generally variable part selects is considered as bad verilog.