Visual C++易挥发的
Visual C++ 中“易失性”的 MSDN 文档表明,除了确保读取始终从内存中读取以及写入始终相应地写入之外,写入具有“释放语义”,读取具有“获取语义”。
“易失性”的 C 规范包括第二部分(不要进行疯狂的优化),但不包括第一部分(内存栅栏)。
Visual C++ 中是否有任何方法可以仅获得“C”易失性行为,而无需内存栅栏?
我想强制一个变量始终位于堆栈上的固定位置,但我不想在每次对其进行赋值时占用内存栅栏的开销。
有没有简单的方法可以使用 Visual C++ 源代码来做到这一点?
The MSDN docs for "volatile" in Visual C++ indicate that writes have "release semantics" and that reads have "acquire semantics", in addition to ensuring that reads always read from memory and that writes always write accordingly.
The C spec for "volatile" includes the second part (don't do crazy optimizations), but not the first part (a memory fence).
Is there any way in Visual C++ to get the "C" volatile behaviour only, without the memory fence?
I want to force a variable to always be on the stack, in a fixed spot, but I don't want to take the overhead of a memory fence on every assignment to it.
Is there any easy way to do that with Visual C++ source?
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在 x86 上,在读取和写入易失性内存位置时,不会在程序集级别创建内存栅栏,因为在该平台上,每个加载都具有获取语义,并且每个存储都具有释放语义。因此,对于 x86 上的 MSVC,
易失性
指令只是指示编译器防止加载和存储的重新排序,具体取决于您是从标记为易失性
的内存位置写入还是读取。 >。在 IA64 架构上,您只会遭受内存栅栏的“惩罚”,因为该平台的内存排序模型不能确保加载和存储的获取和释放语义。
请记住,此行为是 MSVC 特定的,而不是
易失性
的标准化语义。更新:根据 @ildjarn 的说法,您还会在 Windows 8 的 ARM 上看到内存栅栏,因为该平台也有像 IA64 这样的弱有序内存一致性模型。
On x86 there are no memory fences created at the assembly level on reads and writes to a
volatile
memory location since on that platform every load has acquire semantics, and every store has release semantics. Therefore for MSVC on x86, thevolatile
directive simply directs the compiler to prevent the reordering of loads and stores depending on if you are writing or reading from the memory location that was markedvolatile
.You would only incur the "penalty" of a memory fence on the IA64 architecture, since there the memory ordering model of the platform does not ensure acquire and release semantics for loads and stores.
Keep in mind this behavior is MSVC-specific, and is not a standardized semantic of
volatile
.Update: According to @ildjarn you would also see a memory fence on ARM with Windows 8 since that platform also has a weakly ordered memory-consistency model like IA64.