需要帮助阅读图表
我试图理解MIPS（单周期数据路径）中的寄存器写入操作的图表。我不明白为什么我们需要将解码器的输出与写入启用信号进行AND操作？我不知道它将如何启用特定寄存器。请帮我解决一下。 
谢谢。
I am trying to understand the diagram for register write operation in MIPS(Single Cycle Data Path). I do not get why do we need to AND the output of the decoder to the write enable signal? I am not getting how would it enable the specific register. Please help me out with it.
Thanks.
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图中有几个不一致的地方。 “n-to-2^n”解码器应该有
n输入和2^n输出。对于这样的解码器，寄存器的数量应该是2^n。解码器输入指定要写入的地址（即寄存器）。对于任何
2^n可能的寄存器编号，解码器的相应输出将设置为1，所有其他输出设置为0>。“写”信号可能是由时钟驱动的。
AND 门的目的是使“写”信号传播到正确的寄存器（只有一个！）寄存器是通过输入解码器的地址来选择的，如上所述。
选定的寄存器将锁存到“寄存器数据”，最有可能在时钟的上升沿。所有剩余的寄存器将保持其当前值，因为它们的
C输入始终保持为0。There are several inconsistencies in the diagram. The "n-to-2^n" decoder should have
ninputs and2^noutputs. With such a decoder, the number of registers should be2^n.The decoder inputs specify the address (i.e. the register) to be written to. For any of the
2^npossible register numbers, the corresponding output of the decoder will be set to1, with all other outputs set to0.The "write" signal is probably driven off a clock.
The purpose of the
ANDgates is to make the "write" signal propagate to the correct register (just the one!) The register is chosen by the address fed into the decoder, as described above.The selected register will latch onto the "register data", most probably on the rising edge of the clock. All the remaining registers will keep their present values, since their
Cinputs will remain at0throughout.