Makefile - 两个不同的目标

发布于 2024-12-02 10:45:10 字数 265 浏览 0 评论 0原文

我正在为一个应用程序制作一个 Makefile,它可以通过两种不同的方式构建。其中一个(我们可以称之为基本输出),有一个输出叫做a.out1。第二个输出是通过显式传递参数来生成的 - 例如“make a.out2”并启用一些功能,这些功能由源中的预处理器打开。 因此,目标文件与 a.out1 中的目标文件不同。在构建 a.out2 时,是否有一个选项可以在 Makefile 中指定,以明确表示如果 a.out1 已经构建,则使用目标文件清除它并构建 a.out1 (和依赖的 objs)? (当然反之亦然) 谢谢

I am making a Makefile for an application, which can be build in two different ways. One (we can call it basic output), there is an output called a.out1. Second output is made by explicitly passing argument to make - e.g. `make a.out2' and enables some features, which are turned on by preprocessor in sources.
Thus object files are different than object files from a.out1. Is there an option to specify in Makefile when building a.out2, to explicitly say that if a.out1 is already build, clear it with object files and build a.out1 (and depended objs)? (and of course vice versa)
thanks

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琉璃梦幻 2024-12-09 10:45:10

如果您不介意有单独的目标文件(例如 objA1.oobjA2.o),那么可以采用以下方法:

OBJECTS = objA objB objC

OBJ1 = $(addsuffix 1.o,$(OBJECTS))
OBJ2 = $(addsuffix 2.o,$(OBJECTS))

a.out1: $(OBJ1)
    link $^ together one way

a.out2: $(OBJ2)
    link $^ together another way

obj%1.o: %.cc
    build $@ from 
lt; by rule 1

obj%2.o: %.cc
    build $@ from 
lt; by rule 2

如果两个可执行文件(>a.outa.out2)需要不同的对象文件,您可以这样做:

COMMON_OBJECTS = objA objB objC

OBJ1 := $(addsuffix 1.o,$(COMMON_OBJECTS))
OBJ2 := $(addsuffix 2.o,$(COMMON_OBJECTS))

OBJ1 += objD
OBJ2 += objE objF

如果两个构建命令(以两种不同方式构建对象)之间的差异是一些简单的事情,比如改变编译器参数,你可以使最后两条规则稍微简单一点:

obj%1.o: CC_FLAGS += $(FLAGS_FOR_ONE)
obj%2.o: CC_FLAGS += $(FLAGS_FOR_TWO)

obj%1.o obj%2.o: %.cc
    build $@ from 
lt; using $(CC_FLAGS)

同样,如果链接命令除了链接器参数之外相同(或完全相同):

a.out1: $(OBJ1)
a.out1: LINKER_FLAGS += $(L_FLAGS_FOR_ONE)

a.out2: $(OBJ2)
a.out1: LINKER_FLAGS += $(L_FLAGS_FOR_TWO)

a.out1 a.out2: $(OBJ1)
    link $^ together using $(LINKER_FLAGS)

If you don't mind having separate object files (e.g. objA1.o and objA2.o), then here's a way to do it:

OBJECTS = objA objB objC

OBJ1 = $(addsuffix 1.o,$(OBJECTS))
OBJ2 = $(addsuffix 2.o,$(OBJECTS))

a.out1: $(OBJ1)
    link $^ together one way

a.out2: $(OBJ2)
    link $^ together another way

obj%1.o: %.cc
    build $@ from 
lt; by rule 1

obj%2.o: %.cc
    build $@ from 
lt; by rule 2

If the two executables (a.out and a.out2) need different object files, you can do this:

COMMON_OBJECTS = objA objB objC

OBJ1 := $(addsuffix 1.o,$(COMMON_OBJECTS))
OBJ2 := $(addsuffix 2.o,$(COMMON_OBJECTS))

OBJ1 += objD
OBJ2 += objE objF

If the difference between the two build commands (for building the objects in the two different ways) is something simple, like changing a compiler argument, you can make the last two rules a little simpler:

obj%1.o: CC_FLAGS += $(FLAGS_FOR_ONE)
obj%2.o: CC_FLAGS += $(FLAGS_FOR_TWO)

obj%1.o obj%2.o: %.cc
    build $@ from 
lt; using $(CC_FLAGS)

Likewise if the linking command is the same except for a linker argument (or exactly the same):

a.out1: $(OBJ1)
a.out1: LINKER_FLAGS += $(L_FLAGS_FOR_ONE)

a.out2: $(OBJ2)
a.out1: LINKER_FLAGS += $(L_FLAGS_FOR_TWO)

a.out1 a.out2: $(OBJ1)
    link $^ together using $(LINKER_FLAGS)
萌︼了一个春 2024-12-09 10:45:10

这个怎么样?

a.out2: clear1
    #other commands

a.out1: clear2 
    #other commands

How about this?

a.out2: clear1
    #other commands

a.out1: clear2 
    #other commands
~没有更多了~
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