首次在 Pentium M 中引入：...间接分支预测器。
间接分支预测器
由于间接分支从寄存器加载其分支目标，而不是像直接分支那样立即可用，因此它们非常难以预测。 Core 的间接分支预测器是一个表，存储前端遇到的每个间接分支的首选目标地址的历史信息。因此，当前端遇到间接分支并预测它被采用时，它可以要求间接分支预测器将其定向到该分支可能需要的 BTB 中的地址。

http://www.realworldtech.com/page.cfm?ArticleID=rwt051607033728& ;p=3

间接分支预测首先在 Intel 的 Prescott 微架构和后来的 Pentium M 中引入。
所有分支错误预测中有 16-50% 是间接的（平均 29%）。间接分支错误预测的真正价值在于许多较新的脚本或高级语言，例如使用解释器的 Ruby、Perl 或 Python。其他常见的间接分支常见罪魁祸首包括虚函数（在 C++ 中使用）和对函数指针的调用。

http://www.realworldtech.com/page.cfm?ArticleID=RWT102808015436& ;p=5

AMD 采用了其中一些改进；例如，在巴塞罗那和更高版本的处理器中添加间接分支预测器数组。然而，K8 的分支预测器比 Core 2 更旧且不太准确。

http://www.agner .org/optimize/microarchitecture.pdf

3.12 旧处理器上的间接跳转
间接跳转、间接调用和返回每次都可能到达不同的地址。这
间接跳转或间接调用的预测方法是，在早于 PM 的处理器中
K10，只是为了预测它将到达与上次执行相同的目标。

和相同的 pdf，第 14 页

间接跳转预测
间接跳转或调用是具有两种以上可能的控制转移指令
目标。 C++ 程序可以生成间接跳转或调用...虚函数。间接跳转或调用是在汇编中生成的
指定寄存器或内存变量或索引数组作为跳转的目的地
或致电指令。许多处理器只为间接跳转或调用创建一个 BTB 条目。
这意味着它总是被预测会达到与上次相同的目标。
随着使用多态类的面向对象编程变得越来越普遍，
预测具有多个目标的间接调用的需求日益增长。这可以做到
通过为遇到的每个新跳转目标分配一个新的 BTB 条目。历史
缓冲区和模式历史表必须有空间容纳多于一位的信息
每次跳跃事件都是为了区分两个以上可能的目标。
PM 是第一个实现此方法的 x86 处理器。第 p 上的预测规则。 12 仍然
适用于可预测的理论最大周期的修改
完美的是 mn，其中 m 是每次间接跳跃的不同目标的数量，因为有
mn 个不同的可能的 n 长度子序列。然而，这个理论最大值不能
如果超过 BTB 或模式历史表的大小，则无法达到。

Agner 的手册对许多现代 CPU 中的分支预测器以及每个制造商的 cpu (x86/x86_64) 中预测器的演变进行了较长的描述。

还有很多理论上的“间接分支预测”方法（查看Google学术）；甚至 wiki 也说了一些关于它的内容 http://en.wikipedia.org/wiki/Branch_predictor#Prediction_of_indirect_jumps< /a> /

对于来自 agner 微型的 Atoms：

间接分支的预测
根据我的测试，Atom 没有间接分支的模式预测器。间接
预测分支将达到与上次相同的目标。

因此，对于低功耗，间接分支预测并不是那么先进。 Via Nano 也是如此：

预计间接跳跃将到达与上次相同的目标。

我认为，低功耗 x86 的较短管道具有较低的惩罚，7-20 个刻度。

AMD processor in the early-gigahertz era had a 40 cycle penalty every time you called a function

Huh.. so large..

There is an "Indirect branch prediction" method, which helps to predict virtual function jump, IF there was the same indirect jump some time ago. There is still a penalty for first and mispredicted virt. function jump.

Support varies from simple "predicted right if and only if the previous indirect branch was exactly the same" to very complex two-level tens or hundreds entries with detecting of periodic alternation of 2-3 target address for single indirect jmp instruction.

There was a lot of evolution here...

http://arstechnica.com/hardware/news/2006/04/core.ars/7

first introduced with the Pentium M: ... indirect branch predictor.
The indirect branch predictor
Because indirect branches load their branch targets from a register, instead of having them immediately available as is the case with direct branches, they're notoriously difficult to predict. Core's indirect branch predictor is a table that stores history information about the preferred target addresses of each indirect branch that the front end encounters. Thus when the front-end encounters an indirect branch and predicts it as taken, it can ask the indirect branch predictor to direct it to the address in the BTB that the branch will probably want.

http://www.realworldtech.com/page.cfm?ArticleID=rwt051607033728&p=3

Indirect branch prediction was first introduced with Intel’s Prescott microarchitecture and later the Pentium M.
between 16-50% of all branch mispredicts were indirect (29% on average). The real value of indirect branch misprediction is for many of the newer scripting or high level languages, such as Ruby, Perl or Python, which use interpreters. Other common indirect branch common culprits include virtual functions (used in C++) and calls to function pointers.

http://www.realworldtech.com/page.cfm?ArticleID=RWT102808015436&p=5

AMD has adopted some of these refinements; for instance adding indirect branch predictor arrays in Barcelona and later processors. However, the K8 has older and less accurate branch predictors than the Core 2.

http://www.agner.org/optimize/microarchitecture.pdf

3.12 Indirect jumps on older processors
Indirect jumps, indirect calls, and returns may go to a different address each time. The
prediction method for an indirect jump or indirect call is, in processors older than PM and
K10, simply to predict that it will go to the same target as last time it was executed.

and the same pdf, page 14

Indirect jump prediction
An indirect jump or call is a control transfer instruction that has more than two possible
targets. A C++ program can generate an indirect jump or call with... a virtual function. An indirect jump or call is generated in assembly by
specifying a register or a memory variable or an indexed array as the destination of a jump
or call instruction. Many processors make only one BTB entry for an indirect jump or call.
This means that it will always be predicted to go to the same target as it did last time.
As object oriented programming with polymorphous classes has become more common,
there is a growing need for predicting indirect calls with multiple targets. This can be done
by assigning a new BTB entry for every new jump target that is encountered. The history
buffer and pattern history table must have space for more than one bit of information for
each jump incident in order to distinguish more than two possible targets.
The PM is the first x86 processor to implement this method. The prediction rule on p. 12 still
applies with the modification that the theoretical maximum period that can be predicted
perfectly is mn, where m is the number of different targets per indirect jump, because there
are mn different possible n-length subsequences. However, this theoretical maximum cannot
be reached if it exceeds the size of the BTB or the pattern history table.

Agner's manual has a longer description of branch predictor in many modern CPUs and the evolution of predictor in cpus of every manufacturer (x86/x86_64).

Also a lot of theoretical "indirect branch prediction" methods (look in the Google scholar); even wiki said some words about it http://en.wikipedia.org/wiki/Branch_predictor#Prediction_of_indirect_jumps /

For Atoms from the agner's micro:

Prediction of indirect branches
The Atom has no pattern predictor for indirect branches according to my tests. Indirect
branches are predicted to go to the same target as last time.

So, for low power, indirect branch prediction is not so advanced. So does Via Nano: