如何管理没有后缀的 make 目标？

发布于 2024-11-29 02:36:00 字数 688 浏览 1 评论 0原文

我有一个生成多个目标的 make 文件。类似这样的：

target-a: target-a.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@
target-b: target-b.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@
target-c: target-c.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@

实际的构建过程（上面缩写为 $(BUILD_TOOL) ）是一个多行的事情，涉及编译器、脚本和各种诸如此类的东西，但可以说，构建过程作用于第一个目标依赖项($<) 并生成输出目标 ($@)。

这是相当笨拙的。 我下面的内容是否被认为是替换上述内容的安全方法（使用没有后缀的模式规则）？

all: target-a target-b target-c

% : %.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@

make 工具是 GNU，我很乐意使用它强大的扩展。

原文

I've got a make file that generates multiple targets. Something like:

target-a: target-a.src target-include.src
        @$(BUILD_TOOL) -f lt; -o $@
target-b: target-b.src target-include.src
        @$(BUILD_TOOL) -f lt; -o $@
target-c: target-c.src target-include.src
        @$(BUILD_TOOL) -f lt; -o $@

The actual build process (abbreviated as $(BUILD_TOOL) above) is a multiple line thing involving compilers, scripts and various whatnot, but suffice to say, the build process acts on the first target dependency ($<) and produces the output target ($@).

This is quite unwieldly. Would what I've got below be considered a safe way to replace the above (using a pattern rule that doesn't have a suffix)?

all: target-a target-b target-c

% : %.src target-include.src
        @$(BUILD_TOOL) -f lt; -o $@

The make tool is GNU, and I'm content to use it's powerful extensions.

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雨后咖啡店 2024-12-06 02:36:00

如果target是一个文字字符串，renierpost的解决方案非常好。如果不是（或者即使是），这将起作用：

TARGETS := target-a target-b target-c

all: $(TARGETS)

$(TARGETS): % : %.src target-include.src
    @$(BUILD_TOOL) -f lt; -o $@

请注意，此规则不会构建您不想要的目标，甚至不会构建target-include。

If target is a literal string, renierpost's solution is very good. If it isn't (or even if it is) this will work:

TARGETS := target-a target-b target-c

all: $(TARGETS)

$(TARGETS): % : %.src target-include.src
    @$(BUILD_TOOL) -f lt; -o $@

Note that this rule will not build targets you did not intend, not even target-include.

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再浓的妆也掩不了殇 2024-12-06 02:36:00

这取决于你的 Makefile 的其余部分，但原则上这应该有效，
如果所有文件都在一个目录中。

更好的做法是在目标上使用扩展。

target 是文字字符串吗？在这种情况下，你可以更具体
（并稍微加快规则应用速度，但已经很快了）

all: target-a target-b target-c

target-% : target-%.src target-include.src
    @$(BUILD_TOOL) -f lt; -o $@

如果您想自动推导出 target-a target-b target-c 的名称，通过使用 GNU make 的高级语法将发挥作用> 来自文件系统上的 target-*.src 文件名或类似名称。

It depends on the rest of your Makefile, but in principle this should work,
if all files are in one directory.

It's better practice to use extensions on your targets.

Is target a literal string? In that case, you can be more specific
(and speed up rule application a tiny little bit, but it's fast already) by using

all: target-a target-b target-c

target-% : target-%.src target-include.src
    @$(BUILD_TOOL) -f lt; -o $@

GNU make's advanced syntax will come into play if you want to automatically deduce the names of target-a target-b target-c from the target-*.src filenames on the filesystem or something similar.

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