cpu如何与外设通信？
我假设CPU可以直接访问主板的BIOS和RAM。（如果我错了，请纠正我）
但是CPU如何与其他硬件（如硬盘、扩展卡、外围设备、其他BIOS等）通信？
我了解操作系统及其驱动程序，但它们是软件——它们位于 RAM 中。 cpu如何在硬件层面与所有这些硬件进行通信？ 不是仅限于主板的BIOS和RAM吗？
i assume cpu has direct access to motherboard's BIOS and RAM.(correct me if i'm wrong)
But how does cpu communicate with other hardware like hdds, expansion cards, peripherals, other BIOSes etc.?
I know about OS and its drivers, but they are software- they're in RAM.
How does cpu communicate with all this hardware on hardware level?
Isn't it limited to only motherboard's BIOS and RAM?
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在较旧的架构中，外设是通过单独的机制访问的，而内存访问则使用特殊的 I/O 指令。在 x86 上，有（现在仍然有！）用于在 CPU 和外设之间传输字节的“输入”和“输出”指令。外设有指定地址，例如键盘为 0x80。简化很多，执行“in 0x80”将从键盘控制器读取一个字节到CPU寄存器“AL”。
在现代架构中，外设的访问方式与内存类似：通过总线上的映射内存地址。您不应该将总线视为访问内存的方式。它更多的是一种寻址各个外设的方法，其中内存 (RAM/DDR) 只是其中一种类型。例如，您可能在地址 0x00000000..0x7fffffff 处有 2GB RAM。之后，您的显卡可能位于 0x80000000..0x80001fff。总线控制器（PCIe 或其他控制器）知道哪个地址范围到达哪个外设。
内存通常比较特殊，因为它可以被缓存，因此对内存的单独读/写往往不会直接转换为对 RAM 芯片的单独读/写。外设被标记为特殊 - CPU 访问应该完全按照程序中写入的方式进行到外设。
您与外围设备交谈的语言几乎是临时的，具体取决于设备。一般主题是外设被映射到内存中的某个位置（例如，0x80000000 代表上面的几 KB），状态和操作的各个位由不同的字（通常是 32 或 64 位）控制。位于 0x80000000 的串行端口的虚构示例：
再说一次，完全是为了举例而编造的，但真正的串行端口（uart）并没有那么不同。
问题是，由于虚拟内存的存在，您实际上不会在现代操作系统中看到任何上述内存布局。上面的地址将被称为“物理内存地址”（或总线地址）——到达总线的实际地址。相反，CPU 看到的是虚拟内存地址。各个外设需要映射到虚拟地址空间。解释起来有点复杂，可能最好在另一个问题中解释，但关键是您不太可能通过现代操作系统中的实际物理地址来访问外围设备。
In older architectures, peripherals were accessed via a separate mechanism to memory access with special I/O instructions. On x86, there were (and still are!) "in" and "out" instructions for transferring bytes between the CPU and a peripheral. Peripherals were given addresses, for example 0x80 for the keyboard. Simplifying a lot, doing "in 0x80" would read a byte from the keyboard controller to CPU register "AL".
On modern architectures, peripherals are accessed in a similar way to memory: via mapped memory addresses on a bus. You shouldn't think of a bus as a way to access memory. It's more a way to address individual peripherals, of which memory (RAM/DDR) is just one type. For example, you might have 2GB of RAM at addresses 0x00000000..0x7fffffff. After that you might have a graphics card at 0x80000000..0x80001fff. The bus controller (PCIe or whatever) knows which address ranges go to which peripheral.
Memory is usually special in that it can be cached, so individual reads/writes to memory tend not to translate directly to individual reads/writes to the RAM chips. Peripherals are marked as special - CPU accesses should go out to the peripheral exactly as written in your program.
The language you talk to peripherals with is pretty much ad-hoc depending on the device. The general theme is that the peripheral is mapped somewhere in memory (e.g 0x80000000 for a few KB as above), with individual bit of state and actions controlled by different words (usually 32 or 64bit). A mythical example of a serial port at 0x80000000:
Again, totally made up just for sake of example, but a real serial port (uart) isn't all that different.
The trouble is you won't actually see any of the above memory layout in a modern OS, because of virtual memory. The addresses above would be referred to as "physical memory addresses" (or bus addresses) - the actual addresses that go out onto the bus. The CPU instead sees virtual memory addresses. Individual peripherals will need to be mapped into virtual address space. This is kind of complicated to explain and probably best off in another Question, but the point is you're unlikely to access a peripheral by its actual physical address in a modern OS.
当然，接受的答案是准确的，但也许 DrStrangeLove 打算解决其他问题，或者至少这个问题可以容纳另一个答案。事实上，当有人问“外设在硬件层面如何与CPU通信？”时，我想答案应该提到I/O模块（比如大家都知道的I/O适配器）的作用。强调这一点很重要，因为与 I/O 设备通信所需的部分逻辑嵌入在 I/O 模块中，从而减少了执行 I/O 操作时 CPU 的注意力。在这个问题的背景下，这听起来与我相关，因为它询问了 I/O 操作的硬件方面，而适配器是抽象 I/O 设备本质的硬件部件，向 CPU 隐藏了它们的复杂性（并且也来自操作系统）。例如，磁盘适配器隐藏磁盘的几何形状，使 CPU 免于运行旋转磁盘板、定位柱面并等待正确的扇区通过读/写磁头所需的逻辑。类似的推理也适用于视频适配器、网卡等其他设备。简而言之，如果没有 I/O 模块，I/O 任务将会压垮 CPU。引用斯托林斯的话：
此外，正如 John Ripley 正确指出的那样，I/O 空间的映射方式与 RAM 相同。事实上，外设可以直接映射到内存地址空间（称为MMIO，内存映射I/O），或者单独的地址空间（PMIO，端口映射 I/O，也称为“隔离 I/O”，因为与 MMIO 不同，I/O 地址与计算机 RAM 的地址完全分离这就是为什么你有。使用in和out指令与使用PMIO的设备进行通信）。
如上所述，MMIO 和 PMIO 将 I/O 设备视为内存位置 - 这是硬件处理 I/O 操作的本质，但这里值得提及一些进一步的细节，以便获得涉及的丰富概念负载。输入/输出。由于每个适配器都有有限的地址范围，我们必须了解这些内存位置作为数据缓冲区工作，这意味着您一次只有几个字节（“数据块”）与设备通信。因此，CPU 通常不直接使用从这些内存位置读取的数据：首先，通过相应的地址从 I/O 设备读取数据，然后将该数据存储到 RAM 中，并且仅然后CPU就可以使用它了。为了实现这一点，请考虑 CPU 必须执行的大型二进制文件：磁盘适配器具有由其 I/O 寻址空间限制的有限缓冲区（注意，我不是指适配器的内部缓冲区，而是指其CPU 看到的地址空间），因此适配器从磁盘读取一些数据，并在缓冲区填满时通过中断警告 CPU；接下来，CPU 会中断正在执行的操作，读取缓冲区，将缓冲区的内容复制到 RAM 中，并向适配器发出信号，表明它可以继续从磁盘获取更多数据。重复此循环，直到二进制文件完全加载到 RAM 中。从那时起，读取操作被声明完成并且文件最终可以被执行。
这个周期称为中断驱动的 I/O，完全发生在硬件中（有一些操作系统支持处理中断），但请注意还有另外两个选项来执行 I/O 操作。还可以采用所谓的 PIO（可编程 I/O），其中 CPU 不使用中断机制，而是通过循环连续池化控制器，直到逐块收集所有所需信息（当最后一个块被检索到，循环结束）。中断驱动的 I/O 和 PIO 都会浪费 CPU 时间（尤其是后者），并且很早以前就被直接内存访问 (DMA) 所取代，DMA 允许 I/O 设备将其数据直接写入（或读取）到（或来自）RAM，按照CPU的指示。由于其池化性质，我相信 PIO 完全在软件中实现，但在这一点上我可能是错的。我必须指出的是，虽然 DMA 使 PIO 和中断驱动的 I/O 过时了，但我不确定这两者是否被现代架构所禁止。
The accepted answer is accurate, of course, but perhaps DrStrangeLove intended to address something else or, at least, the question acommodates another answers. In fact, when someone asks "How does the peripherals communicate with the CPU on the hardware level?", I think the answer should mention the role of the I/O modules (like the I/O adapters everyone knows about). This is important to emphasize because part of the logic required to speak with the I/O devices is embedded within the I/O modules, decreasing the need for CPU's attention when performing I/O operations. This sounds relevant to me in the context of the question because it asks about the hardware aspects of the I/O operations, and the adapters are hardware pieces that abstract the intrinsicacies of the I/O devices, hidding their complexities from the CPU (and from the OS as well). For example, disk adapters hide the disks' geometry aspects, freeing the CPU from running the logic required to spin the disks' plates, locate a cylinder and wait for the correct sector to pass under the read/write heads. Similar reasonings apply to other devices as video adapters, network cards and so on. In a nutshell, without the I/O modules the I/O tasks would overwhelm the CPU. To quote Stallings:
Besides, as John Ripley correctly stated, there is an I/O space that is mapped in the same fashion as the RAM is. Indeed, the peripherals could be mapped directly into the memory address space (which is known as MMIO, Memory Mapped I/O), or in a separated adress space (PMIO, Port-Mapped I/O, which is also called "isolated I/O" because, unlike MMIO, the I/O addresses are entirely separated from those of the computer's RAM. That's why you have to use the in and out instructions to communicate with devices using PMIO).
By the above, either MMIO and PMIO treat I/O devices as memory positions - which is the essence of how the hardware deals with I/O operations, but some further details are worth mentioning here in order to get the rich conceptual load involved in I/O. Since each adapter have a limited address range, we must understand that such memory positions work as data buffers, which means that you have only a few bytes ("data blocks") to communicate with the device at a time. For this reason, it is common that the CPU does NOT use directly the data it reads from those memory positions: first, the data is read from the I/O device via the corresponding address, next this data is stored into the RAM and only then the CPU can use it. In order to get that, think in a large binary file that the CPU must execute: the disk adapter have a limited buffer bounded by its I/O addressing space (note I am not referring to the internal buffers of the adapter, but to its address space as seen by the CPU), so the adapter reads some data from the disk and warns the CPU when the buffer fills via an interrupt; next, the CPU interrupts whatever it is doing, reads the buffer, copies the buffer's content into the RAM and signals the adapter it can continue to bring more data from the disk. This cycle repeats until the binary file if completely loaded into the RAM. From that point, the read operation is declared finished and the file can finally be executed.
This cycle is is called interrupt-driven I/O and occurs totally in hardware (with some OS support to handle the interrupts), but please note that there are another two options to perform I/O operations. It is also possible to employ the so called PIO (Programmable I/O) where instead of using the interrupt mechanism, the CPU continuously pools the controller via a loop until all the required information is gathered, block-by block (when the last block is retrieved, the loop ends). Both interrupt-driven I/O and PIO wastes CPU time (particularly the latter) and have been superseded long time ago by Direct Memory Access (DMA), which allows the I/O device write (or read) its data directly to (or from) the RAM as instructed by the CPU. Because of its pooling nature, I believe PIO is fully implemented in software, but I could be wrong at this point. I have to remark that, although DMA made PIO and interrupt-driven I/O outdated, I am not sure both were banned from modern architetures.
这取决于您所说的“直接访问”是什么意思。 CPU 内核通过总线与主内存 (RAM) 进行通信。 （内核可能可以更直接地访问相对少量的内存（高速缓存或寄存器），但这是一个不同的问题。）CPU 还通过总线与外设进行通信。您可能听说过的某些类型的总线包括通用串行总线（USB；通常用于外部设备）、PCI、前端总线（一种连接 CPU 内核和主内存的总线）或串行 ATA（SATA；经常使用）对于硬盘等设备）。
ETA：我在下面的评论中提到，设备驱动程序处理 CPU 和外设之间的硬件级通信。通信的实际机制可能涉及使用地址空间的特定部分来传输数据（内存-映射 I/O），因此从设备中物理读取或写入设备看起来就像访问普通内存一样。设备驱动程序还处理 CPU 如何响应来自设备的中断。
That depends on what you mean by "direct access". A CPU core communicates with main memory (RAM) over a bus. (The core may have more direct access to relatively small amounts of memory (cache or registers), but that's a different issue.) The CPU also communicates with peripherals via buses. Some types of buses you might have heard about are universal serial bus (USB; typically for external devices), PCI, front-side bus (a type of bus connecting CPU cores and main memory), or Serial-ATA (SATA; often used for devices like hard disks).
ETA: I mentioned that in my comment below that device drivers handle the hardware-level communication between CPU and peripheral. The actual mechanics of the communication can involve using specific portions of the address space to transfer data (memory-mapped I/O), so that physically reading from or writing to a device looks like accessing ordinary memory. The device driver also deals with how a CPU will respond to interrupts from a device.
如果我错了，请纠正我。
基本上，外围设备使用PCI（外围组件互连）与处理器进行通信，它是一种将设备直接连接到处理器的总线。
当通过外围设备发出命令（例如按下键盘上的任何按钮）时，它会转换为二进制代码并以高速缓存的形式存储在内存中，然后由处理器完成该特定功能所需的执行。
Please correct me if I am wrong.
Basically peripheral device communicate with processor using PCI(peripheral component interconnect), it a type of bus that connect the device directly to the processor.
when a command is given through a peripheral device (say any button press on keyboard) it is converted into binary code and stored in memory in the form of cache memory and then required execution for that particular function is done by the processor.