corei3 中的硬件预取

发布于 2024-11-23 19:26:52 字数 44 浏览 3 评论 0原文

corei3是否支持通过硬件预取器进行硬件预取?如果是,如何启用/禁用它?

Does corei3 support hardware prefetching through hardware prefetcher? If yes, how do I enable/disable it?

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谁许谁一生繁华 2024-11-30 19:26:52

Intel Core i3 处理器绝对支持硬件预取,尽管 Intel 的文档在细节方面往往非常薄弱。品牌名称“Core i3”指的是基于“Nehalem”和“Sandy Bridge”的处理器,因此您必须检查具体型号才能知道您正在处理的是哪一款。

更复杂的是,较新的英特尔处理器(Nehalem/Westmere/Sandy Bridge)具有多种不同的硬件预取器——《英特尔架构软件开发人员手册》第 3B 卷(出版物 253669)中至少提到了三种。表 30-25“MSR_OFFCORE_RSP_x 请求类型字段定义”提到“DCU 预取”和“L2 预取器”。附录 A-2、表 A-2 中也提到了这些事件,其中描述了 Core i7、i5 和 i3 处理器的性能计数器事件。表 A-2 中的事件 4EH 提到存在“L1 流媒体和基于 IP (IPP) 的硬件预取器”。附录 A.4、表 A-6 的相应条目(针对事件 4EH)中还有关于此主题的更多内容,该条目描述了 Westmere 处理器的性能计数器。

同一文档中的附录 B-2、表 B-3 讨论了英特尔酷睿微架构的 MSR(模型特定寄存器),但看起来其中许多都延续到了较新的版本中。寄存器 1A0h 显示 4 位控制预取行为:

  • 位 9:硬件预取器禁用
  • 位 19:相邻缓存行预取禁用
  • 位 37:DCU 预取器禁用
  • 位 39:IP 预取器禁用

用于启用和禁用预取器的工具在以下内容中讨论:
如何以编程方式禁用硬件预取?

Intel Core i3 processors definitely support hardware prefetching, though Intel's documentation tends to be very weak on details. The brand name "Core i3" refers to both "Nehalem" based and "Sandy Bridge" based processors, so you have to check the specific model number to know which one you are dealing with.

To make things more complicated, newer Intel processors (Nehalem/Westmere/Sandy Bridge) have several different hardware prefetchers -- at least three are mentioned in the Intel Architecture Software Developer's Manual, Volume 3B (publication 253669). Table 30-25 "MSR_OFFCORE_RSP_x Request Type Field Definition" mentions "DCU prefetch" and "L2 prefetchers". These are also mentioned in Appendix A-2, Table A-2, which describes the performance counter events for Core i7, i5, and i3 processors. Event 4EH in Table A-2 mentions that there are both "L1 streamer and IP-Based (IPP) HW prefetchers". There are a few more words on this topic in the corresponding entry (for event 4EH) in Appendix A.4, Table A-6, which describes the performance counters for Westmere processors.

Appendix B-2, Table B-3 in the same document discusses the MSRs (Model Specific Registers) for the Intel Core Microarchitecture, but it looks like many of these carry over into newer versions. Register 1A0h shows that 4 bits control prefetching behavior:

  • Bit 9: Hardware Prefetcher Disable
  • Bit 19: Adjacent Cache Line Prefetch Disable
  • Bit 37: DCU Prefetcher Disable
  • Bit 39: IP Prefetcher Disable

Tools to enable and disable prefetchers are discussed in:
How do I programmatically disable hardware prefetching?

戏蝶舞 2024-11-30 19:26:52

是的,Core i3/i7 机器中确实存在硬件预取器,但您不能在 i3/i7 中禁用它们。通过 BIOS 更改 msr 位 (2) 来禁用预取 (1) 的两种方法。 Intel 停止支持 i3/i7 中的这两种禁用方式。

评论链接: https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors 某些 Intel 上的 H/W 预取器控制的披露处理器 - Vish Viswanathan(英特尔),2014 年 9 月 24 日

本文公开了 MSR 设置,可用于控制基于以下微架构的英特尔处理器上可用的各种硬件预取器:Nehalem、Westmere、Sandy Bridge、Ivy Bridge、Haswell 和 Broadwell。

上述处理器支持 4 种类型的硬件预取器来预取数据。有 2 个与 L1 数据缓存关联的预取器(也称为 DCU DCU 预取器、DCU IP 预取器)和 2 个与 L2 缓存关联的预取器(L2 硬件预取器、L2 相邻缓存行预取器)

每个内核上都有一个地址为 0x1A4 的型号特定寄存器 (MSR),可用于控制这 4 个预取器。该寄存器中的位 0-3 可用于启用或禁用这些预取器。该MSR的其他位被保留。

Yes, Hardware prefetcher does exist in Core i3/i7 machine, but you CAN'T disable them in i3/i7. Two ways to disable the prefetching (1) by changing msr bit (2) through bios. Intel stopped supporting both ways to disable in i3/i7.

Link from comment: https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors Disclosure of H/W prefetcher control on some Intel processors - Vish Viswanathan (Intel), September 24, 2014

This article discloses the MSR setting that can be used to control the various h/w prefetchers that are available on Intel processors based on the following microarchitectures: Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, and Broadwell.

The above mentioned processors support 4 types of h/w prefetchers for prefetching data. There are 2 prefetchers associated with L1-data cache (also known as DCU DCU prefetcher, DCU IP prefetcher) and 2 prefetchers associated with L2 cache (L2 hardware prefetcher, L2 adjacent cache line prefetcher).

There is a Model Specific Register (MSR) on every core with address of 0x1A4 that can be used to control these 4 prefetchers. Bits 0-3 in this register can be used to either enable or disable these prefetchers. Other bits of this MSR are reserved.

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