VHDL：FlipFlop D 代码中的错误

发布于 2024-11-18 08:12:08 字数 828 浏览 2 评论 0原文

我正在用VHDL做一个D触发器这是代码：

LIBRARY STD,WORK;
USE STD.standard.all;
entity FlipFlopD is 
port(
  input, clock :in bit;
  output :out bit
);
end FlipFlopD;

--Architecture of the entity
Architecture FlipFlopDfunc of FlipFlopD is 
begin 
  PROCESS (clock)
  BEGIN
    IF (clock’EVENT AND clock=‘1’) THEN 
      output <= input; 
    END IF;
  END PROCESS;
end FlipFlopDfunc;

这些是我尝试合成它时遇到的错误：

Line 16. Unexpected symbol read: ?.
Line 16. Unexpected symbol read: ?.
Line 16. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR

第 16 行中的错误对我来说很奇怪，因为我没有看到任何“？”此行中的符号：

IF (clock’EVENT AND clock=‘1’) THEN

有谁知道如何纠正它？有谁知道如何处理此错误解析错误，意外的IDENTIFIER，期待COMMA或CLOSEPAR？

顺便说一句，我正在使用 ISE 9.2 进行设计感谢您的帮助。

原文

I am doing a D flip flop with VHDL
This is the code:

LIBRARY STD,WORK;
USE STD.standard.all;
entity FlipFlopD is 
port(
  input, clock :in bit;
  output :out bit
);
end FlipFlopD;

--Architecture of the entity
Architecture FlipFlopDfunc of FlipFlopD is 
begin 
  PROCESS (clock)
  BEGIN
    IF (clock’EVENT AND clock=‘1’) THEN 
      output <= input; 
    END IF;
  END PROCESS;
end FlipFlopDfunc;

These are errors I get when I try to synthesize it:

Line 16. Unexpected symbol read: ?.
Line 16. Unexpected symbol read: ?.
Line 16. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR

The error in line 16 is extrange to me because I don´t see any '?' symbol in this line:

IF (clock’EVENT AND clock=‘1’) THEN

Does anyone know how to correct it?
Does anyone know what to do with this error parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR?

By the way, I am doing my design using ISE 9.2
Thank you for your help.

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仙女 2024-11-25 08:12:08

您确定使用了正确类型的单引号 (') 符号吗？如果它们在你的 VHDL 代码中是这样的，我猜它们是错误的。

IF (clock'EVENT AND clock='1') THEN

Are you sure you use the correct type of single quote (') signs? If they are like this in your VHDL code I guess they are wrong.

IF (clock'EVENT AND clock='1') THEN

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内心荒芜 2024-11-25 08:12:08

我从上面剪切并粘贴了您的代码，正如 bmk 所说，刻度线是错误的。

您也可以将该行写为 :-

if rising_edge(clock) then

但您必须使用以下库和包。

library IEEE;
use IEEE.std_logic_1164.all;

I cut and pasted your code from above, and as bmk says, the ticks are wrong.

You can also write that line as :-

if rising_edge(clock) then

But you would than have to use the following library and package.

library IEEE;
use IEEE.std_logic_1164.all;

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要走就滚别墨迹 2024-11-25 08:12:08

除了 @bmk 和 @George 的正确观察之外，您还应该删除这些行：

LIBRARY STD,WORK;
USE STD.standard.all;

VHDL 标准规定这些行已经隐含在任何 VHDL 文件中。
这些条款对您的代码没有任何影响，但它们会将您识别为新手。

In addition to the correct observation by @bmk and by @George, you should remove these lines:

LIBRARY STD,WORK;
USE STD.standard.all;

The VHDL standard dictates that these lines are already implied in any VHDL file.
Those clauses do not have any effect on your code, but they will identify you as a novice.

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