makefile 中的变量目标

发布于 2024-11-18 06:05:12 字数 562 浏览 3 评论 0原文

我正在尝试编译一组目标。然而它似乎只做了第一个。下面是显示错误的我的 makefile 的删减。

  OBJECTS = abc def ghi
  SOURCES = abc.c def.c ghi.c

  $(OBJECTS):     $(SOURCES)
          @echo target is $@, source is $<

在 shell 中，

  $ touch abc.c def.c ghi.c
  $ make

当我运行 make 时，我得到以下输出：

  target is abc, source is abc.c

所以它似乎只运行第一个目标。

如果我替换 $<使用 $^，输出为：

  target is abc, source is abc.c def.c ghi.c

我的问题，是否可以像 (%: %) 模式那样对变量执行扩展？

原文

I am trying to compile set of targets. However it only seems to do the first one. Below is a cut down of the my makefile that shows the error.

  OBJECTS = abc def ghi
  SOURCES = abc.c def.c ghi.c

  $(OBJECTS):     $(SOURCES)
          @echo target is $@, source is lt;

In shell,

  $ touch abc.c def.c ghi.c
  $ make

When I run make I get the following output:

  target is abc, source is abc.c

So it only seems to be running the first target.

If I replace $< with $^, the output is:

  target is abc, source is abc.c def.c ghi.c

My question, is it possible to perform expansions on variables like with the (%: %) pattern?

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一杯敬自由 2024-11-25 06:05:12

试试这个：

  OBJECTS = abc def ghi

  all: $(OBJECTS)

  $(OBJECTS):%:%.c
          @echo target is $@, source is lt;

问题是

Try this:

  OBJECTS = abc def ghi

  all: $(OBJECTS)

  $(OBJECTS):%:%.c
          @echo target is $@, source is lt;

The trouble was

The default target (which is what Make chooses if you just type `make`) is the first target in the makefile, which was `abc`.
You made all sources prerequisites of every object. That is, all three sources were prerequisites of `abc`. They were also prerequisites of `def` and of `ghi`.

~没有更多了~