我的 VHDL 正弦函数生成器出了什么问题？
library IEEE;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SineGen is
Port (clock : in std_logic;
dac_ab_vpp : in integer range 0 to 4095;
dac_cd_vpp : in integer range 0 to 4095;
sine_dac_ab : out std_logic_vector(11 downto 0);
sine_dac_cd : out std_logic_vector(11 downto 0));
end SineGen;
architecture Behavioral of SineGen is
subtype slv is std_logic_vector(11 downto 0);
begin
process(clock)
variable count : integer range 0 to 255 := 0;
variable temp_dac_ab : integer range 0 to 4095 := 0;
variable temp_dac_cd : integer range 0 to 4095 := 0;
begin
if rising_edge(clock) then
我尝试了一切，归结为接下来的两行使输出始终为零，我不明白为什么。它应该是具有正弦函数的输出。 （count 是每个周期 256 个样本。n 是位数。）以下格式是否有效？
-- A*sin (2PI/2^n * count)
temp_dac_ab := dac_ab_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));
temp_dac_cd := dac_cd_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));
if count < 256 then
count := count + 1;
else
count := 0;
end if;
sine_dac_ab <= conv_std_logic_vector(temp_dac_ab, slv'length);
sine_dac_cd <= conv_std_logic_vector(temp_dac_cd, slv'length);
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SineGen is
Port (clock : in std_logic;
dac_ab_vpp : in integer range 0 to 4095;
dac_cd_vpp : in integer range 0 to 4095;
sine_dac_ab : out std_logic_vector(11 downto 0);
sine_dac_cd : out std_logic_vector(11 downto 0));
end SineGen;
architecture Behavioral of SineGen is
subtype slv is std_logic_vector(11 downto 0);
begin
process(clock)
variable count : integer range 0 to 255 := 0;
variable temp_dac_ab : integer range 0 to 4095 := 0;
variable temp_dac_cd : integer range 0 to 4095 := 0;
begin
if rising_edge(clock) then
I tried everything and it comes down to that the next two lines makes the output always zero, and I don't understand why. It should've been an output with a sine function. (count is the 256 samples per period. n is the number of bits.) Are the following in valid format?
-- A*sin (2PI/2^n * count)
temp_dac_ab := dac_ab_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));
temp_dac_cd := dac_cd_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));
if count < 256 then
count := count + 1;
else
count := 0;
end if;
sine_dac_ab <= conv_std_logic_vector(temp_dac_ab, slv'length);
sine_dac_cd <= conv_std_logic_vector(temp_dac_cd, slv'length);
end if;
end process;
end Behavioral;
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评论（2）
除了 @brianreavis 指出的之外，您不想将分数
math_2_pi/real(256)转换为整数，因为它始终为 0。所以：In addition to what has been pointed out by @brianreavis, you don't want to convert the fraction
math_2_pi/real(256)to an integer, since that will always be 0. So:我对我的 VHDL 真的很生疏，但我认为你想要这个：（
你不想舍入/投射来自
sin的浮点数，直到你将它与dac_ab_vpp 相乘之后/dac_cd_vpp）I'm realllyyy rusty with my VHDL, but I think you're wanting this:
(You don't want to round / cast the float coming from
sinuntil after you multiply it withdac_ab_vpp/dac_cd_vpp)