这些赋值语句有什么作用？

发布于 2024-11-10 12:38:23 字数 283 浏览 0 评论 0原文

我无法理解这段代码末尾的两行：

input [15:0] offset ;
output [31:0] pc;
output [31:0] pc_plus_4;
reg [31:0] pc;
wire [31:0] pcinc ;

assign pcinc = pc +4 ;
assign pc_plus_4 = {pc[31],pcinc};
    
assign branch_aadr = {0,pcinc + {{13{offset[15]}},offset[15:0],2'b00}};

原文

I can't understand the two lines at the end of this code:

input [15:0] offset ;
output [31:0] pc;
output [31:0] pc_plus_4;
reg [31:0] pc;
wire [31:0] pcinc ;

assign pcinc = pc +4 ;
assign pc_plus_4 = {pc[31],pcinc};
    
assign branch_aadr = {0,pcinc + {{13{offset[15]}},offset[15:0],2'b00}};

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似狗非友 2024-11-17 12:38:23

如果您不熟悉花括号 {}，它们是连接运算符。您可以在 IEEE Std for Verilog 中了解它们（例如，1800-2009，第 11.4.12 节）。

assign pc_plus_4 = {pc[31],pcinc};

这会将 pc 的 MSB 与 pcinc 的所有位连接起来，以组合 pc_plus_4 信号。然而，在这种情况下，由于 pcinc 和 pc_plus_4 都是 32 位宽，因此 pc[31] 被忽略。一个好的 linting 工具会通知您 RHS 是 33 位，LHS 是 32 位，并且最高有效位将丢失。该行可以更简单地编码为：

assign pc_plus_4 = pcinc;

最后一行是我正在使用的一个模拟器的编译错误。您没有显式声明 branch_aadr 信号的宽度，并且 0 常量的宽度未指定。

If you are unfamiliar with curly braces {}, they are concatenation operators. You can read about them in the IEEE Std for Verilog (for example, 1800-2009, Section 11.4.12).

assign pc_plus_4 = {pc[31],pcinc};

This concatenates the MSB of pc with all bits of pcinc to assemble the pc_plus_4 signal. However, in this case, since pcinc and pc_plus_4 are both 32 bits wide, pc[31] is ignored. A good linting tool will notify you that the RHS is 33 bits and the LHS is 32 bits, and that the most significant bit will be lost. The line can be more simply coded as:

assign pc_plus_4 = pcinc;

The last line is a compile error for one simulator I'm using. You did not explicitly declare the width of the branch_aadr signal, and the width of the 0 constant is unspecified.

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绝影如岚 2024-11-17 12:38:23

最后一行还包含一个复制运算符，它使用两组花括号。

{13{offset[15]}}

这将复制位 offset[15] 十三次。看起来作者在将 offset 添加到 pcinc 之前对其进行了符号扩展。更好的方法可能是将 offset 声明为有符号的。

//Three ways to replicate bits
wire [3:0] repeated;
wire       value;

//These two assignments have the same effect
assign repeated = {4{value}};                 //Replication operator
assign repeated = {value,value,value,value};  //Concatenation operator

//These four taken together have the same effect as the above two
assign repeated[3] = value; //Bit selects
assign repeated[2] = value;
assign repeated[1] = value;
assign repeated[0] = value;

The last line also contains a replication operator, which uses two sets of curly braces.

{13{offset[15]}}

This replicates the bit offset[15] thirteen times. It looks like the author is doing a sign extension on offset before adding it to pcinc. A better way might be to declare offset as signed.

//Three ways to replicate bits
wire [3:0] repeated;
wire       value;

//These two assignments have the same effect
assign repeated = {4{value}};                 //Replication operator
assign repeated = {value,value,value,value};  //Concatenation operator

//These four taken together have the same effect as the above two
assign repeated[3] = value; //Bit selects
assign repeated[2] = value;
assign repeated[1] = value;
assign repeated[0] = value;

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