VHDL实体和架构设计
借助 Ada，我可以使用 .ads 和 .adb 文件将模块化单元拆分为规范和主体。
是否可以将VHDL实体和体系结构分开？如果是这样，是否有命名约定或推荐的样式来执行此操作？这些实体可以放置在自定义库/包中吗？
With Ada I can split my modular units into specification and body with .ads and .adb files.
Is it possible to separate VHDL entity and architecture? If so, is there a naming convention or recommended style for doing this? And can the entities be placed in a custom library/package?
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库
一切都被编译到库中。默认情况下，这称为“工作”，但您可以覆盖它。不过，我很少需要使用它 - 如果存在命名空间冲突，它偶尔对外部 IP 很有用。正如 Chiggs 评论的那样，使用库创建名称空间是一种很好的做法。大多数合成器现在可以处理多个库，尽管情况并非总是如此。所有模拟器都可以（据我所知）。设置它们还涉及更多麻烦（您必须告诉编译器它们都在哪里）。
也许是一个例子 - 假设你有一个 i2c 控制器和一个 spi 控制器。您可以调用这两个块
controller并将它们编译到自己的库中，称为i2c和spi，然后像这样实例化它们：或者您可以调用它们
i2c_controller和spi_controller并执行以下操作：库与硬盘文件夹并不“完全相同”。它们由 VHDL 编译器管理，因此您可以使用该工具使用的任何语法来创建和映射它们。
例如，使用 Modelsim，
vlib在文件系统中的特定位置创建一个库（因此此时它看起来确实像一个文件夹），并且vmap告诉编译器如何映射针对文件系统特定位的use some_lib;子句。实体、架构、包
您可以将实体和架构（甚至每个实体多个架构）分离到多个文件中，或将它们保留在一个文件中。将
架构保存在单独的文件中意味着当您重新编译它时，您不会重新编译实体，这意味着您不必重新编译实例化它的所有内容。与
packages和package body类似 - 单独文件中的主体意味着您可以只重新编译该部分而无需重新编译其他所有内容。请注意，package不适用于放入实体。（另外 - Modelsim 有一个
-just开关，允许您将所有内容保留在一个文件中，并仅编译选定的部分文件，例如，只是architecture和/或body部分）摘要
work库Libraries
Everything gets compiled into a library. By default this is called "work", but you can override this. I rarely have to use that though - it's occasionally useful with external IP if there are namespace clashes. As Chiggs commented, using libraries to create namespaces is a good practice. Most synthesizers can deal with multiple libraries now, although it wasn't always the case. All the simulators can (as far as I know). There's also a bit more hassle involved in setting them up (you have to tell the compiler where they all are).
maybe an example - say you have an i2c controller and an spi controller. You could call both blocks
controllerand compile them into their own libraries calledi2candspiand then instantiate them like this:or you could call them
i2c_controllerandspi_controllerand do:And libraries are not "just the same" as hard disk folders. They are managed by the VHDL compiler, so you create and map them using whatever syntax the tool uses.
For example with Modelsim,
vlibcreates a library at a particular place in the filesystem (so it does look like a folder at this point) andvmaptells the compiler how to map ause some_lib;clause to a particular bit of the filesystem.Entities, architectures, packages
You can separate your entity and architecture (or even more than one architecture per entity) into multiple files, or keep them in one file. Keeping the
architecturein a separate file means that when you recompile it, you don't recompile theentity, which means you don't have to recompile everything that instantiates it.Similarly with
packagesandpackage bodys - bodies in a separate file means you can just recompile that part without recompiling everything else. Note thatpackages are not for putting entities in.(Aside - Modelsim has a
-justswitch that allows you to keep everything in one file and just compile selected bits of the files, for example, just thearchitectureand/orbodypart(s))Summary
worklibrary实体和架构是独立的设计单元。它们可以位于同一个文件中，也可以位于单独的文件中。文件扩展名保持不变：通常为
.vhd，但.vhdl也是可能的。对于文件名，没有普遍接受的命名约定。 （实际上有数百种约定，因此这与根本没有约定一样有用）任何事情都有效；例如，您可以使用myEntity.vhd和myEntity_RTL.vhd。您可以编译在自己的库中编写的实体和架构。您可以使用您的公司名称作为图书馆名称。
不过，不要将库与包混淆！包是保存可重用声明的编译单元。库是一组命名的编译单元。
Entity and architecture are separate design units. They can be in the same file or they can be in separate files. The file extensions remain the same: usually
.vhdbut.vhdlis also possible. For the file names, there is no generally accepted naming convention. (There are hundreds of conventions really, so that is as useful as no convention at all) Anything works; as an example, you could usemyEntity.vhdandmyEntity_RTL.vhd.You can compile entities and architectures that you write in your own library. You might use your company name as library name.
Don't confuse libraries with packages, though! A package is a compilation unit that holds reusable declarations. A library is a named set of compilation units.