有gnu make的配置文件吗?

发布于 2024-11-07 18:37:12 字数 131 浏览 0 评论 0原文

我想告诉 make 它应该始终使用 -j4 选项,即使我没有在命令行中指定它。通常我会在一些配置文件(即~/.makerc)中执行此操作。

gnu make 是否存在这样的文件?

I want to tell make that it shall always use -j4 option even if I didn't specify it vie command line. Normally i would do this in some configuration file (i.e. ~/.makerc).

Does such file exist for gnu make?

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落在眉间の轻吻 2024-11-14 18:37:12

阅读有关 $(MAKEFLAGS) 变量的信息:

export MAKEFLAGS=j4

然而,这个可能会干扰基于递归 make 的构建(无论如何,明智的人都不会使用递归 make!),通过干扰 GNU make 与其通信的能力子品牌。

因此,更明智的方法可能是包装脚本或别名或 shell 函数。

Have a read about the $(MAKEFLAGS) variable:

export MAKEFLAGS=j4

However this will likely interfere with recursive-make-based builds (not that sensible people are using recursive make anyway!), by interfering with GNU make's ability to communicate with its sub-makes.

So the more sensible approach is probably a wrapper script or an alias or shell function.

过去的过去 2024-11-14 18:37:12

嗯,是和否——通常您会使用 包含文件。< /a> 将常用配置项放在一个文件中,例如 common.mk 并添加

include common.mk

到 makefile 的顶部。如果该标志没有匹配的方法来从 make 文件内部配置它,您可以使用一个函数

function mk {
    make -j4 $*
}

Well, yes and no --- normally you would use an include file. Put your common configuration items together in a file, say common.mk and add

include common.mk

at the top of your makefile. If the flag doesn't have a matching way to configure it from inside the make file, you can use a function

function mk {
    make -j4 $*
}
残龙傲雪 2024-11-14 18:37:12

它不存在,但您可以通过递归调用 make 来完成此操作。

例如:


Makefile:

-include $(HOME)/.makerc

.DEFAULT_GOAL: all

# This will handle a default goal if make is just called without any target
all:
    $(MAKE) $(MAKE_OPTIONS) -f Makefile.real $(MAKECMDGOALS)

# This handles all targets and passes it through
%:
    $(MAKE) $(MAKE_OPTIONS) -f Makefile.real $(MAKECMDGOALS)


$(HOME)/.makerc:

MAKE_OPTIONS := -j4

It doesn't exist, but you can do this by having a recursive call into make.

For example:


Makefile:

-include $(HOME)/.makerc

.DEFAULT_GOAL: all

# This will handle a default goal if make is just called without any target
all:
    $(MAKE) $(MAKE_OPTIONS) -f Makefile.real $(MAKECMDGOALS)

# This handles all targets and passes it through
%:
    $(MAKE) $(MAKE_OPTIONS) -f Makefile.real $(MAKECMDGOALS)

$(HOME)/.makerc:

MAKE_OPTIONS := -j4
拍不死你 2024-11-14 18:37:12

我想对约翰·马歇尔的答案中暗示的解决方案进行一些扩展。

您可以简单地将单行包装脚本放在 $PATH 中较早的位置,其中包含以下内容:(

#!/bin/bash
$(type -ap make | sed -n 2p) -j4 "$@"

该脚本不必命名为 make,这将使它更简单,但我发现它很方便。)

我认为这比其他方法更好,原因如下:

  • MAKEFLAGS 方法不同,它不会破坏递归构建(这是实际上根据我的经验很常见)。
  • include .makerc 方法不同,它可以在本地应用,而无需以任何方式更改任何现有的 makefile 或您的工作流程。
  • 与 shell 别名或函数方法不同,它与 shell 无关(不会将您绑定到任何特定 shell),并且可以在您可能必须使用的任何其他构建脚本中工作,只要您在同一环境中启动它们即可。

I would like to expand a bit on the solution hinted in John Marshall's answer.

You can simply put a one-line wrapper script somewhere earlier in the $PATH with the following contents:

#!/bin/bash
$(type -ap make | sed -n 2p) -j4 "$@"

(The script doesn't have to be named make, and that would make it simpler, but I find it convenient if it is.)

I would argue that this is better than the other approaches for the following reasons:

  • Unlike MAKEFLAGS approach, it does not break recursive builds (which are actually quite common in my experience).
  • Unlike include .makerc approach, it can be applied locally without changing any existing makefiles or your workflow in any way.
  • Unlike shell alias or function approach, it is shell-agnostic (doesn't tie you to any particular shell) and works in any additional build scripts that you might have to use, too, as long as you launch them in the same environment.
聽兲甴掵 2024-11-14 18:37:12

我喜欢 John Marshall 建议的 MAKEFLAGS 方法来代替 make 支持自动 .makerc 项目配置文件之类的东西。但是,我不想记住事先获取 .env 或类似的环境变量(然后取消设置它们)。

解决方案是将 MAKEFLAGS 赋值放在 Makefile 本身的顶部:

#!/usr/bin/env make

MAKEFLAGS=s

.PHONY: foo
foo:
    echo "hello, make"

运行它:

$ make foo
hello, make

与不使用 MAKEFLAGS=... 运行相比代码>行:

$ make foo
echo "hello, make"
hello, make

I like the MAKEFLAGS approach suggested by John Marshall in lieu of make supporting something like an automatic .makerc project config file. However, I didn't want to have to remember to source a .env or similar environment variables beforehand (and unsetting them afterward).

A solution to this is to put the MAKEFLAGS assignment at the top of the Makefile itself:

#!/usr/bin/env make

MAKEFLAGS=s

.PHONY: foo
foo:
    echo "hello, make"

Run it:

$ make foo
hello, make

Compared to running without the MAKEFLAGS=... line:

$ make foo
echo "hello, make"
hello, make
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