makefile 中的条件 OR
我想在我的 makefile 中启用详细编译，但我不知道如何创建条件 OR。
让我解释一下：我希望能够通过设置 V=1 或 VERBOSE=1 来指定详细编译代码>.我想保持 VERBOSE=1 可用，因为我们有一些使用它的脚本（并且使用其他 makefile 只知道 VERBOSE），
所以结果一定是这两个命令是相同的：
make all VERBOSE=1 # pain to write
make all V=1
现在，我的 makefile 今天看起来像这样：
ifdef VERBOSE
[issue compilation commands with verbose mode]
endif
我想要实现的目标接近于 C 中的预处理器：
if defined(VERBOSE) || defined(V)
[issue compilation commands with verbose mode]
endif
你知道怎么做吗？
I'd like to enable a verbose compilation in my makefile, but I can't figure out how to make a conditional OR.
Let me explain: I want to be able to specify a verbose compilation either by setting V=1 or VERBOSE=1. I want to keep VERBOSE=1 available because we have some scripts that make use of it (and use other makefiles only aware of VERBOSE)
So the result must be that these two commands are the same:
make all VERBOSE=1 # pain to write
make all V=1
Now, my makefile looks like this today:
ifdef VERBOSE
[issue compilation commands with verbose mode]
endif
What I'd like to achieve is close to the preprocessor in C:
if defined(VERBOSE) || defined(V)
[issue compilation commands with verbose mode]
endif
Do you know how to do that?
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我确实喜欢这样：
类似于 $(strip 方法，但使用更直观的 $(or 关键字
I do like this:
Similar to the $(strip approach, but using the more intuitive $(or keyword
...然后...
...then...
我喜欢尼尔·巴特沃斯的方法，但如果你真的想按照你描述的风格来做，这会给你或：
I like Neil Butterworth's approach, but if you really want to do it in the style you describe, this will give you OR:
据我所知，GNU make 中的条件内容不允许使用 OR 和 ANDS。你总是可以这样做：
但我不明白为什么你需要首先引入 V 的（几乎不自我记录）定义。
As far as I know, the conditional stuff in GNU make doesn't allow for ORs and ANDS. You could always do something like:
but I don't see why you need to introduce the (hardly self documenting) define of V in the first place.
好吧，真的晚了，但我遇到了这个，并想为其他正在寻找如何向 makefile 添加逻辑的人添加另一个解决方案：基本上，在 shell 中执行逻辑，并以这种方式获取输出。
它看起来更复杂，但如果你有一个包含许多 and 和 or 的 if 语句，这提供了很大的灵活性，并且比嵌套的 $(and .. $(or ...)) 语句更容易阅读。
Ok, really late to the party, but I came across this, and wanted to add another solution for others who were looking how to add logic to makefiles: basically, do the logic in a shell, and get the output that way.
it seems more convoluted, but if you have an if statement with many ands and ors, this offers a lot of flexibility, and would be easier to read than nested $(and .. $(or ...)) statements.