Verilog 始终使用 (*) 符号进行阻止
我有一个关于如何在 Verilog 模块中编写 always 块的简单问题。
如果我的 Verilog 模块中有以下输入：
input [31:0] PCplus4 ; // Value of PC + 4
input [31:0] A; // Value A, i.e. RSbus (Use Forwarded Value)
input [31:0] B; // Value B, i.e. RTbus (Use Forwarded Value)
input [31:0] IMM; // Extended Immediate Value
input [25:0] TARGET; // Target Address for Jumps
input [3:0] BR; // Branch Selector Input
如果我使用
always @ (*)
代替
always @ (PCplus4 or A or B or IMM or TARGET or BR)
Is this always @ (*) 语法对所有版本的 Verilog 都有效吗？
I have a simple question regarding how to write an always block in a Verilog module.
If I have the following inputs in my Verilog module:
input [31:0] PCplus4 ; // Value of PC + 4
input [31:0] A; // Value A, i.e. RSbus (Use Forwarded Value)
input [31:0] B; // Value B, i.e. RTbus (Use Forwarded Value)
input [31:0] IMM; // Extended Immediate Value
input [25:0] TARGET; // Target Address for Jumps
input [3:0] BR; // Branch Selector Input
Is there any difference if I use
always @ (*)
instead of
always @ (PCplus4 or A or B or IMM or TARGET or BR)
Is this always @ (*) syntax valid for all versions of Verilog?
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always @(*)语法于 2001 年添加到 IEEE Verilog 标准中。所有现代 Verilog 工具（模拟器、综合等）都支持此语法。以下是 LRM (1800-2009) 的引述：
因此，您的两行代码可能是等效的（这取决于
always块主体中的代码）。但是，@*语法更易于维护。The
always @(*)syntax was added to the IEEE Verilog Std in 2001. All modern Verilog tools (simulators, synthesis, etc.) support this syntax.Here is a quote from the LRM (1800-2009):
So, your two lines of code may be equivalent (it depends on the code in the body of your
alwaysblock). However, the@*syntax is easier to maintain.always @(*)是 2001 年标准修订版中对该语言的补充。所有最新版本的质量工具都支持它。我不担心在旨在任意重用的代码中使用该构造，但是，有可能遇到不支持always @(*)的旧工具，特别是当内部实用程序涉及。always @(*)was an addition to the language in the 2001 revision of the standard. It is supported by all recent releases of quality tools. I have no concerns about using the construct in code intended for arbitrary reuse, however, there is a possibility of encountering an old tool that does not supportalways @(*), especially when in-house utilities are involved.尽管两者是等效的，但使用always@(*)可以避免任何模拟综合不匹配。
假设敏感度列表中有 15 个信号，如下所示：
现在假设设计者错误地错过了此列表中的 a14。综合工具忽略这一事实，并假设该块内 RHS 上的所有信号都在灵敏度列表中来综合代码。而模拟工具的行为有所不同，因为它取决于敏感度列表。
Though both are equivalent, using
always@(*)avoids having any simulation-synthesis mismatch.Lets assume you have 15 signals in the sensitivity list as below:
Now assume that the designer has missed having a14 in this list by mistake. The synthesis tool ignores this fact and synthesizes the code assuming all the signals on RHS within this block are in the sensitivity list. Whereas the simulation tool behaves differently since it depends on the sensitivity list.
它只是列出always 块所依赖的所有线路的快捷方式。这些电线是“敏感列表”。使用它的一个优点是，合成代码不太可能关心您在敏感度列表中放入的内容（除了 pedge 和 negedge），因为电线将“物理”连接在一起。模拟器可能依赖该列表来选择哪些事件应导致块执行。如果您更改模块并忘记更新列表，您的模拟可能会偏离实际的综合行为。
It's just a shortcut for listing all of the wires that the always block depends on. Those wires are the "sensitivity list". One advantage of using it is that synthesized code is unlikely to care what you put in the sensitivity list (other than posedge and negedge) because the wires will be "physically" connected together. A simulator might rely on the list to choose which events should cause the block to execute. If you change the block and forget to update the list your simulation might diverge from the actual synthesized behavior.
对于第一个问题......我想说这取决于在第二种情况下，这些是您认为可以更改的唯一输入，这将导致输出触发。理想情况下，最好使用 *，因为它表示“对于输入的任何更改”，而且它有助于避免冗长的代码。
对于第二个问题......它是在verilog -2001中引入的，从那时起它就被广泛使用。
For the 1st question....i would say that depends if in second scenario that those are the only inputs you feel can change which will cause a triggering to the output. Ideally it would be better to use * as it indicates "for any change in inputs", Also it is helpful in avoiding verbose code.
For the second question.....it was introduced in verilog -2001 and ever since then it has been used extensively.
*表示包含所有输入，因此相当于写入所有输入。如果您希望模块是非顺序组合电路，则使用
*符号也很有用，因为每当任何输入更改时，总会有一些东西发生变化。*means all the inputs included, so it is equivalent to writing all the inputs.Using the
*symbol is also useful with always if you want your module to be combinational circuit not sequential, since there is something always changing whenever any input is changed.