我对MAKE的理解正确吗？
以 GNU make 应用程序为例，当我创建 makefile 时，它类似于 Visual Studio 项目文件，因为它包含编译应用程序所需的文件列表和其他项目。 makefile 包含编译器的路径以及编译操作中可能使用的所有文件的路径。 MAKE 应用程序读取 makefile 并将源代码组合成 1 个文件，然后编译器读取该文件并将其转换为相关的汇编/机器代码。
#include 指令是一个指令，它告诉 make 文件： “将此文件的内容包含到您要提供给编译器的较大文件的这一点，然后使用当前文件恢复”。
MAKE 应用程序还告诉编译器在编译完成后在哪里“发出”编译操作的结果。在这方面，Visual Studio .csproj 文件在技术上是一个基于 XML 的 makefile，用于 Microsoft 特定的 MAKE 应用程序。
这种对makefile的理解正确吗？
Taking the GNU make application as an example, when I create a makefile it is likened to a Visual Studio project file in that it contains the list of files and other items needed to compile an application. The makefile contains the path to the compiler as well as the path to all the files that could possibly be used in the compiling operation. The MAKE application reads the makefile and combines the sources into 1 file which the compiler then reads and converts into the relevant assembly/machine code.
The #include directive is a directive that tells the make file to:
"include the contents of this file into this point of the larger file that you're making to feed to the compiler then resume with the current file".
The MAKE application also tells the compiler where to "emit" the result of the compile operation once the compiling is completed. In this regard a Visual Studio .csproj file is technically a XML based makefile for a Microsoft specific MAKE application.
Is this understanding of makefiles correct?
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大约是的。然而，还有许多细节值得挑剔。
这相当接近准确。
makefile 通常不包含编译器的路径，尽管它可以包含。它将包含编译中可能使用的文件列表。
这不是很准确。细节有所不同，但聚合不是由 MAKE 完成的，而是由 MAKE 调用的编译器完成的。除了简单的源代码到机器代码转换之外，MAKE 还可用于其他任务。
GNU Make（和 POSIX Make）支持
include指令来合并 makefile 的其他片段。 C 和 C++ 编译器识别#include指令 - 并且 makefile 通常需要了解编译程序所需的标头（由#include指令包含） 。然而，#include是 makefile 中的一个简单注释。makefile 包含有关生成的代码应放置在何处的信息，并告知编译器是否需要知道。
这是对描述的合理近似。
Approximately, yes. However there are numerous details to cavil at.
That is reasonably close to accurate.
The makefile typically does not contain the path to the compiler, though it could. It would contain a list of the files that might be used in the compilation.
This is not very accurate. The details vary, but the aggregation is not done by MAKE, but by the compilers that MAKE invokes. MAKE can be used for other tasks than simple source to machine code translation.
GNU Make (and POSIX Make) supports an
includedirective to incorporate other fragments of a makefile. The C and C++ compilers recognize the#includedirective - and the makefile often needs to be briefed on which headers (included by the#includedirective) are needed to compile the program. However,#includeis a simple comment in a makefile.The makefile contains the information about where the generated code should be placed, and the compiler is told if it needs to know.
That is a reasonable approximation to the description.
具体来说，您是对的，因为 makefile 可以这样使用并且经常如此。通常，make 实用程序按照以下规则解决依赖性，这些规则说明哪些项（主要是文件）依赖于其他项以及要采取哪些步骤（例如编译操作）来满足依赖性。 makefile 中的变量和规则遵循 make 实用程序的语法。
Specifically you are right in that a makefile can be used this way and often are. Generally the make utility resolves dependencies in following rules stating which items (mostly files) depend on others and what steps (e. g. compile operations) are to be taken to fulfill the dependency. Variables and rules within makefiles adhere to the make utility's syntax.