无法推断寄存器... at ...，因为它在时钟边沿之外不保存其值

发布于 2024-11-06 12:36:24 字数 649 浏览 4 评论 0原文

这肯定是刚接触 VHDL 的人最常见的问题，但我不明白我在这里做错了什么！这似乎符合我在正确的状态机设计中看到的所有习惯用法。我正在 Altera Quartus 9.2 中进行编译，无论其价值如何。实际错误是：

“无法推断 [文件] [行] 处的“spiclk_out”寄存器，因为它在时钟边缘之外不保存其值”

ENTITY spi_state_machine IS
    PORT(
            spiclk_internal : IN STD_LOGIC;
            reset : IN STD_LOGIC;
            spiclk_out : BUFFER STD_LOGIC
    );
END spi_state_machine;

PROCESS(spiclk_internal, reset)
BEGIN
    IF reset = '1' THEN
        spiclk_out <= '0';
    END IF;

    IF spiclk_internal = '1' AND spiclk_internal'EVENT THEN --error here
        spiclk_out <= NOT spiclk_out;
    END IF;
END PROCESS;

感谢您的宝贵时间。

原文

This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong here! This seems to conform to all of the idioms that I've seen on proper state machine design. I'm compiling in Altera Quartus 9.2, for what it's worth. The actual error is:

"Can't infer register for "spiclk_out" at [file] [line] because it does not hold its value outside the clock edge"

ENTITY spi_state_machine IS
    PORT(
            spiclk_internal : IN STD_LOGIC;
            reset : IN STD_LOGIC;
            spiclk_out : BUFFER STD_LOGIC
    );
END spi_state_machine;

PROCESS(spiclk_internal, reset)
BEGIN
    IF reset = '1' THEN
        spiclk_out <= '0';
    END IF;

    IF spiclk_internal = '1' AND spiclk_internal'EVENT THEN --error here
        spiclk_out <= NOT spiclk_out;
    END IF;
END PROCESS;

Thanks for your time.

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回首观望 2024-11-13 12:36:24

正如所写，即使 reset 处于活动状态，该过程也会导致 spiclk_out 在 spiclk_internal 边沿进行切换，这不是异步复位触发器的方式应该表现。

你可能想要的是

SPICLK: process(spiclk_internal, reset)
    if reset = '1' then
        spiclk_out <= '0';
    elsif spiclk_internal'event and spiclk_internal='1' then
        spiclk_out <= not spiclk_out;
    end if;
end process SPICLK;

As written, the process would cause spiclk_out to toggle on spiclk_internal edges even when reset is active, which is not how flip-flops with asynchronous resets should behave.

What you probably want is

SPICLK: process(spiclk_internal, reset)
    if reset = '1' then
        spiclk_out <= '0';
    elsif spiclk_internal'event and spiclk_internal='1' then
        spiclk_out <= not spiclk_out;
    end if;
end process SPICLK;

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