Verilog 中 == 和 === 有什么区别？
之间有什么区别：
if (dataoutput[7:0] == 8'bx) begin
和
if (dataoutput[7:0] === 8'bx) begin
执行 dataoutput = 52'bx 后，第二个给出 1，但第一个给出 0。为什么？ （0或1为比较结果。）
What is the difference between:
if (dataoutput[7:0] == 8'bx) begin
and
if (dataoutput[7:0] === 8'bx) begin
After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（5）
Verilog 中的某些数据类型（例如
reg）是 4 态的。这意味着每一位可以是 4 个值之一：0,1,x,z。使用“大小写相等”运算符
===，比较 x，结果为 1。使用
==时，比较结果不为 0，如下所示你说；相反，根据 IEEE Std (1800-2009) 第 11.4.5 节“相等运算符”，结果是 x：Some data types in Verilog, such as
reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z.With the "case equality" operator,
===, x's are compared, and the result is 1.With
==, the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators":在 Verilog 中：
In Verilog:
== 用于比较位（0 或 1）
=== 用于比较所有 4 个状态 (0, 1, x, z)
== 可以综合到硬件（x 或非门）中，但是 === 不能综合，因为 x 不是有效的逻辑电平数字，它实际上具有 0 和 1 之间的电压。 z 本身不是任何逻辑，它表示电路断开。
== For comparing bits (0 or 1)
=== For comparing all 4 states (0, 1, x, z)
== can be synthesized into a hardware (x-nor gate), but === can't be synthesized as x is not a valid logic level in digital, it is infact having voltages in between 0 and 1. And z is not itself any logic, it shows disconnection of the circuit.
正如许多人已经评论的那样，如果信号有 X，“正常”比较运算符可能会导致未知的状态/答案。因此，如果您从可以提供 U 或 X 状态的 RAM 进行比较，并且您想要真正检查匹配，那么您应该使用“===”和“!==”运算符。
请参阅 systemverilog 参考文档中的图片。
As many already commented, in case a signal has an X, the "normal" comparison operator can led to unknow states/answers. Therefore, if you are comparing from a RAM that can deliver U or X states and you want to really check a match, then you should use the "===" and "!==" operators.
See picture from the systemverilog reference documentation.
我会添加一些使用指南（其他答案没有给出；实际上，Karan Shah 确实尝试解决这个问题）。
回顾：什么是四值？
我们通常喜欢在前两个域中操作。
对于模拟，您可以有意将值设置为“X”状态。这些值在综合中不存在。在模拟测试中使用
!==和===非常好，因为它会处理这些值。由于总线信令，在应忽略测试输入时故意将测试输入强制为“x”，可以允许“黑匣子”测试以查看是否有任何输出也变为“x”。然而，大多数综合逻辑是内部的，并且不使用高 Z 值。合成期间不能出现“X”值；尽管它可以是未知的 0/1 值（至少对于 FPGA 综合而言）。因此，对于综合，在大多数情况下最好选择
==和!=。gtkwave 工具包有一个“lxt2miner”程序，可用于寻找复位周期之外的“X”模拟信号。我有这样的构建规则，
因此，应用重置时，值在 t=0 时可能不确定，但不应在该时间之后发生。当然，您还可以通过在测试工具中使用这些运算符来添加对“z”和“x”的检查。
I would add some guidance on use (which other answers don't give; actually, Karan Shah did try to address this).
Review: What is four value?
We normally like to operate in the domain of the first two.
For simulation, you can intentionally set values to the 'X' state. Such values do not exist in synthesis. The use of
!==and===in simulation test is excellent as it will take care of these values. Intentionally forcing test inputs to 'x' when they should be ignored, due to bus signalling, can allow a 'black box' tests to see if any output also become 'x'.However, most logic for synthesis is internal and doesn't use high Z values. An 'X' value cannot occur during synthesis; although it can be an unknown 0/1 value (at least for FPGA synthesis). So, for synthesis, it is better to opt for
==and!=in the majority of the cases.The gtkwave tool kit has an 'lxt2miner' program which can be used to look for 'X' simulation signals beyond the reset cycle. I have a build rule as such,
So, values can be undetermined at t=0 when the reset is applied, but should not occur past that. Of course you can also add checks for 'z' and 'x' by using these operators in a test harness.