使用always@* |意义和缺点
的含义是什么吗
- 你能说一下always@*
使用该语句后是否有任何可能的副作用？
can you say what is the meaning of that
- always @ *
Is there any possible side effects after using that statement ?
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它只是列出
always块所依赖的所有连线的快捷方式。这些电线是“敏感列表”。使用它的一个优点是，合成代码不太可能关心您在敏感度列表中放入的内容（posege和negedge除外），因为电线将“物理”连接一起。模拟器可能依赖该列表来选择哪些事件应导致块执行。如果您更改模块并忘记更新列表，您的模拟可能会偏离实际的综合行为。It's just a shortcut for listing all of the wires that the
alwaysblock depends on. Those wires are the "sensitivity list". One advantage of using it is that synthesized code is unlikely to care what you put in the sensitivity list (other thanposedgeandnegedge) because the wires will be "physically" connected together. A simulator might rely on the list to choose which events should cause the block to execute. If you change the block and forget to update the list your simulation might diverge from the actual synthesized behavior.在SystemVerilog中，我们希望您使用always_comb begin...end而不是always @*。
always@* 的一大缺点是，当你的某些组合逻辑涉及常量时，always@* 可能不会在时间 0 触发，它需要看到信号变化才能触发。 always_comb 保证在时间 0 至少触发一次。
Always_comb 的另一个好处是它内联函数调用。如果调用函数，并且函数体引用未作为参数传递的信号，则 @* 始终不会对该信号敏感。
In SystemVerilog, we would prefer that you use always_comb begin...end instead of always @*.
The big drawback with always@* is that when some of your combinatorial logic involves constants, the always @* may not trigger at time 0, it needs to see a signal change to trigger. always_comb guarantees to trigger at time 0 at least once.
Another benefit of always_comb is that it in-lines function calls. If you call a function, and the body of the function references a signal not passed as an argument, always @* will not be sensitive to that signal.
@Ben Jackson 回答正确。第二部分的答案是没有可能的副作用；我认为这是组合逻辑的推荐实践。
@Ben Jackson answered correctly. The answer to the second part is there are no possible side effects; I consider this a recommended practice for combinatorial logic.