优化 FPGA 实现的管道吞吐量的最佳实践是什么？
例如，如何充分利用重定时和/或 c-slow 来充分利用给定的管道。
通过重定时，一些模块通过将移位寄存器放在输入上（前向寄存器平衡）来获得更好的结果，而其他模块通过将移位寄存器放在输出上（后向寄存器平衡）来获得更好的结果。
现在我使用以下方法：
- 代码 hdl（在 verilog 中）
- 为 特定模块
- 合成、地图、放置和路线（使用 ISE 13.1）
- 查看帖子位置和路线时间 对于要改进的模块，并且在 最大逻辑层数。
- 取这个数量的逻辑电平，并且 对数字做出有根据的猜测 要插入的触发器。
- 插入触发器，使能寄存器 平衡，希望最好的情况
就目前情况而言，这种方法是“hit &”。错过。有时它会得到很好的结果，有时却很糟糕。那么，有什么好的办法可以提高这种重定时的成功率呢？
有什么工具可以对此提供帮助吗？此外，链接、论文和书籍推荐将不胜感激。
How does one for example make the best use of retiming and/or c-slow to make the most of a given pipeline.
With retiming, some modules get better results by putting the shift registers on the inputs (forward register balancing), while other modules do better with shift registers on the output (backward register balancing).
For now I use the following method:
- code hdl (in verilog)
- create timing constraints for the
specific module - synthesize, map, place & route (using
ISE 13.1) - look at post place & route timings
for the module-to-be-improved, and at
the maximum number of logic levels. - take this number of logic levels, and
make an educated guess for the number
of flip-flops to insert. - insert flip-flops, enable register
balancing, hope for the best
As it stands, this method is hit & miss. Sometimes it gets pretty good results, sometimes it's crap. So, what is a good way to improve the success ratio of such retiming?
Are there any tools that can aid in this? Also, links, papers and book recommendations would be much appreciated.
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听起来你的想法是正确的。基于工具的重定时可能有点碰运气。有时，在您认为好的内容之上额外添加 2 或 3 个 FF 会有所帮助。
在另一个极端，当我需要将性能推向极限时，我必须手动平衡管道。这可能是一种痛苦，必须将可读性好的 HDL 代码拆分为可怕的显式逻辑和寄存器 - 但有时我发现它确实必须完成:(需要大量注释和一个非常好的测试平台来确保你没有 最后，有一个“中途之
家”，如果我查看逻辑级别最多的逻辑路径并思考一下代码，我经常会发现它只是一小段代码（也许只是一行）。这可以在不“损害”模块其余部分的可读性的情况下被拉出，有时将该代码拉入其自己的实体中并将额外的触发器放入该实体中可以使自动重新平衡器更好地工作。 。
祝你好运！
Sounds like you have the right ideas. Tool-based retiming can be a bit hit-and-miss. Sometimes putting an extra 2 or 3 FFs above what you think will be good can help.
At the other extreme, when I need to push the performance to the limit, I have to balance the pipeline by hand. This can be a right pain, having to split your nicely readable HDL code into awful explicit logic and registers - but sometimes I find it does just have to be done :( Lots of comments required and a really good testbench to make sure you haven't broken it!
Finally, there is a "half-way house". If I look at the logic path which has the most logic levels and think a bit about the code, I often find that it's only one very small piece of code (maybe just one line). This can be pulled out without "harming" the readability of the rest of the module too badly. And sometimes pulling that code into its own entity and putting the extra flipflops in that entity enables the automatic rebalancer to work better.
Good luck!
不是工具，但您可能会欣赏我关于高性能 FPGA 设计艺术的博客文章。
http://www.fpgacpu.org/log/aug02.html#art
快乐黑客！
Not a tool, but you may appreciate my blog entry on the the Art of High Performance FPGA Design.
http://www.fpgacpu.org/log/aug02.html#art
Happy hacking!