verilog 赋值编译器错误

发布于 2024-11-03 01:30:10 字数 364 浏览 3 评论 0原文

我有一个基本的编译器错误，我无法弄清楚。代码：

module (input [127:0] in1,
        input [2:0] en);
real a1;
if(en==3'b001)
begin
  a1=$bitstoreal(in1[31:0]);
end

错误是：

Error: E:/Modeltech_pe_edu_10.0/examples/FloatingPt.v(20): near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER or '#' or '('

原文

I have a basic compiler error I am not able to figure out.
Code:

module (input [127:0] in1,
        input [2:0] en);
real a1;
if(en==3'b001)
begin
  a1=$bitstoreal(in1[31:0]);
end

The error is :

Error: E:/Modeltech_pe_edu_10.0/examples/FloatingPt.v(20): near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER or '#' or '('

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长途伴 2024-11-10 01:30:10

您在过程构造之外有过程代码。

real a1;
initial
  begin
  if(en==3'b001)
    begin
    a1=$bitstoreal(in1[31:0]);
    end
  end

You have procedural code outside a procedural construct.

real a1;
initial
  begin
  if(en==3'b001)
    begin
    a1=$bitstoreal(in1[31:0]);
    end
  end

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讽刺将军 2024-11-10 01:30:10

如果您尝试设置wire的值或在程序块内设置值（always或initial）用于其他数据类型。

在您的示例中，您缺少 always 块：

always @(*) begin
    if(en==3'b001) begin
        a1=$bitstoreal(in1[31:0]);
    end
end

如果您不确定自己在做什么，则在将总线分配给 real 类型时也可能会遇到问题。您可能需要将其写为 a1 = $itor(in1);

Assignments in Verilog are done by the assign statement if you're trying to set the value of a wire or within a procedural block (always or initial) for other data types.

In your example, you are missing an always block:

always @(*) begin
    if(en==3'b001) begin
        a1=$bitstoreal(in1[31:0]);
    end
end

You also might have a problem assigning a bus to the real type if you're not sure of what you're doing. You might need to write it as a1 = $itor(in1);

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