verilog 在同一根线上驱动信号
我浏览了互联网，找不到我的问题的清晰简洁的答案。我想知道如果我将相同强度的信号驱动到同一根线上，其中一个为逻辑 1，另一个为逻辑 0，会发生什么？如果我想要一个“获胜”的信号，但由于没有更好的词，根据具体情况，我该怎么办？
I looked through internet and couldn't find a clear and concise answer to my question. I want to know what'll happen if I drive same strength signals onto the same wire, one of them being logic 1 and the other being logic 0? What do I do if I want a signal to "win", for lack of a better word, depending on the situation?
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根据您的评论，听起来您想要一辆三态巴士。驱动三态总线的基本结构是：
每个驱动总线的模块都有一个这种形式的驱动程序。任何时候只能断言一个模块的使能；总线协议应该定义如何决定总线的所有权。例如，像I2C这样的串行总线有“主”和“从”；主人总是先说话，奴隶只有在主人要求后才说话。
如果您不希望总线在没有任何驱动时浮动（在模拟中，这显示为 Z 值），您可以将总线声明为
tri0或tri1而不是普通的电线。如果多个模块同时置位启用，或者如果您有多个标准
分配总线 = out;驱动程序尝试在总线上驱动不同的值，则称为“争用”。这将在模拟中显示为 X 值，并可能导致物理设备中的驱动程序损坏。Based on your comment, it sounds like you want a three-state bus. The basic structure to drive a three-state bus is:
Each module driving the bus has a driver of this form. Only one module may have its enable asserted at any time; the bus protocol should define how ownership of the bus is decided. For example, serial buses like I2C have a "master" and a "slave"; the master always talks first, and the slave only talks after it has been requested to by the master.
If you don't want the bus to float when nothing is driving (in simulation, this shows up as a Z value), you can declare the bus as
tri0ortri1rather than a regularwire.If multiple modules have the enable asserted at the same time, or if you have multiple standard
assign bus = out;drivers attempting to drive different values on the bus, it is known as "contention". This will show up as an X value in simulation, and could result in damage to the drivers in a physical device.如果负载是一个简单的网络，它将被分配 StX(Strong X)。
您是否想问如何在 Verilog 中对此进行建模或如何使用 MOS 器件进行此建模？
If the load is a simple net it will be assigned StX(Strong X).
Are you asking how to model this in Verilog or how to do this with MOS devices?