为子目录中的 makefile 名称设置目标变量

发布于 2024-11-01 14:32:34 字数 578 浏览 0 评论 0原文

如何在目标执行期间定义 $(MAKEFILE) 的变量? 基本上,我在子目录中有一些为特定平台“Makefile.aix”命名的 make 文件,而在所有其他目录中只有 Makefile。我想为 $(MAKEFILE) 设置一个在每个子目录中定义的变量。代码看起来像这样。

MAKEFILE = Makefile

SUBDIR = ./sub ./sub2

    ifneq ($(wildcard Makefile),)
            MAKEFILE = Makefile
    else
            MAKEFILE = Makefile.$(PLATFORM)
    endif


    all:;
            @for i in $(SUBDIR);\
                    do (\
                            echo Making $$i ...;\
                            cd $$i;\
                            make -f $(MAKEFILE)\
                    ); done

How can I have the variable for $(MAKEFILE) be defined during target execution?
Basically I have a few make files in subdirectories that are named for a specific platform "Makefile.aix" and just Makefile in all other directories. I would like to set a variable for $(MAKEFILE) that gets defined in each subdirectory. Code would look something like this.

MAKEFILE = Makefile

SUBDIR = ./sub ./sub2

    ifneq ($(wildcard Makefile),)
            MAKEFILE = Makefile
    else
            MAKEFILE = Makefile.$(PLATFORM)
    endif


    all:;
            @for i in $(SUBDIR);\
                    do (\
                            echo Making $i ...;\
                            cd $i;\
                            make -f $(MAKEFILE)\
                    ); done

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评论(3

別甾虛僞 2024-11-08 14:32:34

每个子目录中是否只有一个 Makefile.$(PLATFORM),还是有多个针对不同平台的?
在第一种情况下,您可以这样做:(

SUBDIR = ./sub ./sub2

define script
cd $(1); \
$(MAKE) -f Makefile*

endef

all:
    $(foreach dir, $(SUBDIR), $(call script,$(dir)))

定义中的空行很重要。如果您在行末尾添加分号 $(MAKE) ...,导致一个很长的命令行,包含所有目录的命令,然后将在一个块中执行。)

另一种 script 是(只是个人喜好问题,您更喜欢):

define script
$(MAKE) -C $(1) -f $(notdir $(wildcard $(1)/Makefile*))

endef

如果一个目录中有多个 Makefile.$(PLATFORM) 文件,则变得更加困难。我得再考虑一下这个问题。

更新:为了回应您的评论,类似这样的事情应该有效:

define script
$(MAKE) -C $(1) -f $(notdir $(wildcard $(1)/Makefile $(1)/Makefile.$(PLATFORM)))

endef

Is there just one Makefile.$(PLATFORM) in each subdirectory, or are there several, for different platforms?
In the first case, you could do something like this:

SUBDIR = ./sub ./sub2

define script
cd $(1); \
$(MAKE) -f Makefile*

endef

all:
    $(foreach dir, $(SUBDIR), $(call script,$(dir)))

(The empty line inside the define is significant. It can be omitted, if you add a semicolon at the end of the line $(MAKE) ..., leading to one long command line, containing the commands for all directories, which will then be executed in one chunk.)

An alternative script would be (just a matter of personal preference which you like better):

define script
$(MAKE) -C $(1) -f $(notdir $(wildcard $(1)/Makefile*))

endef

If there are several Makefile.$(PLATFORM) files in a directory it becomes more difficult. I'll have to think about that one some more.

UPDATE: In response to your comment, something like this should work:

define script
$(MAKE) -C $(1) -f $(notdir $(wildcard $(1)/Makefile $(1)/Makefile.$(PLATFORM)))

endef
慕烟庭风 2024-11-08 14:32:34

按照你的逻辑,我建议更新 do () 部分:

                do (\
                        echo Making $i ...;\
                        cd $i;\
                        if [ -f Makefile.$(PLATFORM) ] \
                        then\
                          make -f Makefile.$(PLATFORM) \
                        else\
                          make -f Makefile\
                        fi\
                ); done

这实际上不是 make 风格,但如果没有具体的项目,我无法提出更好的建议

Following your logic, I'd propose update do () section with:

                do (\
                        echo Making $i ...;\
                        cd $i;\
                        if [ -f Makefile.$(PLATFORM) ] \
                        then\
                          make -f Makefile.$(PLATFORM) \
                        else\
                          make -f Makefile\
                        fi\
                ); done

This is actually not a make style, but I can't suggest anything better without specific of your project

尐籹人 2024-11-08 14:32:34

您可以使用 GNU make 的内置函数完成大部分工作,包括目录循环。将以下内容放在中心位置,例如 $(TOP_DIR)/mk/subdir.mk

makefile-for-dir = \
  $(if $(wildcard $(1)/Makefile),Makefile,Makefile.$(PLATFORM))

make-recursive = \
  $(foreach _d,$(1),$(MAKE) -C $(_d) -f $(call makefile-for-dir,$(_d)) && ) :

在启动递归 make 的每个 makefile 中,使用

include $(TOP_DIR)/mk/subdir.mk

SUBDIRS = dir1 dir2 dir3

.PHONY: all
all:
    +@$(call make-recursive,$(SUBDIRS))

You can do most of this, including the loop over directories, using GNU make's built-in functions. Put the following in a central place, say $(TOP_DIR)/mk/subdir.mk:

makefile-for-dir = \
  $(if $(wildcard $(1)/Makefile),Makefile,Makefile.$(PLATFORM))

make-recursive = \
  $(foreach _d,$(1),$(MAKE) -C $(_d) -f $(call makefile-for-dir,$(_d)) && ) :

In each makefile that start recursive makes, use

include $(TOP_DIR)/mk/subdir.mk

SUBDIRS = dir1 dir2 dir3

.PHONY: all
all:
    +@$(call make-recursive,$(SUBDIRS))
~没有更多了~
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