如何在 Quartus II 中分配引脚
我们正在考虑将一些代码转移到 CPLD 或 FPGA 中，以提高速度。我之前曾使用过 Xilinks 及其工具套件，但出于某种原因，我们决定这次使用 Altera，所以我正在尝试习惯 Quartus II。
特别是，我正在寻找一种方法来明确地将引脚分配给我正在使用的芯片。在 Xilinx 中，我会编辑网表文件，但在 Quartus 中找不到这样的东西。有一个程序（Assignments => Pin Planner）可以做到这一点，但它有一个笨重的 GUI，我更喜欢在文本编辑器中编辑引脚，所以我的双重问题是
A ：如何找到存储引脚分配的文件？它没有在项目导航器中的我的文件下列出，但我在 Pin Planner 中分配的引脚在会话之间保持不变，因此它们必须存储在某个地方。
B：这是一个可怕的想法吗？
IDE是Quartus II 10.1 开发套件为MAX II开发板 语言是 VHDL
编辑： 现在，我遇到了尝试通过 USB 与开发套件连接的问题。我正在它上面制作一个串行数据接收器，并给它一个数据输入引脚。开发套件有一个 USB 接收器，因此我尝试将 din 映射到 USB 连接器所在的引脚。根据我的文件（rm_maxII-develop_board-rev1.pdf），USB 连接器位于“Board Designation U13”上，但是当我进入 Pin PLAner 并尝试分配它时，没有 PIN_U13。我怀疑这是 pdf 中的错误，而不是 Pin Planner 中的错误，但由于我以前从未使用过 Altera 产品，所以我很困惑。
We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to Quartus II.
In particular, I am looking for a way to explicityly assign pins to the chip I am using. In Xilinx, I'd edit the netlist file but I can find no such thing in Quartus. There is a program (Assignments => Pin Planner) that does this, but it has a clunky GUI and I'd far prefer to edit the pins in a text editor, so my twofold question is
A: How do I find the file that stores the pin assignment? It's not listed under my files in the project navigator but the pins I've assigned in Pin Planner stay from session to session so they must be stored somewhere.
B: Is this a horrible idea?
IDE is Quartus II 10.1
Development kit is MAX II Development Board
Language is VHDL
EDIT: Right now, I've run into the problem that I'm trying to interface with the Dev Kit through USB. I'm making a serial data receiver on it and have given it a Data In pin. The Dev Kit has a USB receiver so I'm trying to map din to whichever pin the USB connector is on. According to a file I have (rm_maxII-develop_board-rev1.pdf) the USB connector is on "Board Designation U13" but when I go into the Pin PLanner and try to assign that, there is no PIN_U13. I suspect this is an error in the pdf, rather than in Pin Planner but seing as I've never worked with Altera products before, I'm very confused.
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A) 您需要编辑 *.qsf 文件，并添加类似于以下内容的行：
B) 虽然我有时会在设计的早期阶段使用引脚规划器，但在修改引脚时我几乎只直接编辑 qsf 文件，从设计中添加或删除 VHDL 文件等。为了完全安全，在进行较大更改（特别是优化或编译器设置）时，我将确保 Quartus 未运行。自从 Quartus 推出以来我就一直以这种方式工作，没有遇到任何问题。
编译设计后，您可以参考 *.pin 文件来查看 FPGA 的最终引脚排列。特别是，请参阅指示引脚是否手动分配的列，因为任何未专门分配到某个位置的引脚在每次重新编译芯片时都会发生很大变化（如果您已经制作了 PCB，则这不是最佳选择） ！:)。
A) You need to edit the *.qsf file, and add lines similar to the following:
B) While I will sometimes use the pin planner in the early stages of a design, I almost exclusively edit the qsf file directly when modifying pins, adding or removing VHDL files from the design, etc. To be completely safe, when making large changes (particularly to optimization or compiler settings) I will make sure Quartus is not running. I've been working this way with Quartus since it came out, and have not had any problems.
Once your design is compiled, you can refer to the *.pin file to see the final pinout for the FPGA. In particular, refer to the column indicating whether or not the pin is manually assigned, as any pins not specifically assigned to a location will change pretty much every time you recompile the chip (which is sub-optimal if you've already made a PCB! :).