不是有效的左值 - verilog 编译器错误

发布于 2024-10-31 12:43:02 字数 2301 浏览 5 评论 0原文

module fronter ( arc, length, clinic ) ;
 input [7:0] arc;
 output reg [7:0] length ;

 input [1:0] clinic;
 input en0, en1, en2, en3; // 11

 // clock generator  is here

 g_cal A( en0) ;
 g_cal B( en1) ;
 g_cal C( en2) ;
 g_cal D( en3) ;

always @( negedge arc, posedge clk )
  case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

// I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule

module g_cal ( en ) ;

 input en ;
 // some other jobs, calling another instances after making some job

endmodule

当我编译时,编译器给我;

verilog.v:23: error: en0 is not a valid l-value in Numerator.
verilog.v:11:      : en0 is declared here as wire.
verilog.v:24: error: en1 is not a valid l-value in Numerator.
verilog.v:11:      : en1 is declared here as wire.
verilog.v:25: error: en2 is not a valid l-value in Numerator.
verilog.v:11:      : en2 is declared here as wire.
verilog.v:26: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
verilog.v:27: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
segmentation fault

我该如何修复它? 为什么会出错?

编辑: 我已经解决了问题;

   // I erased that line "input en0, en1, en2, en3; // 11"

 // clock generator  is here

 g_cal A(  1'b0) ;
 g_cal B(  1'b0) ;
 g_cal C(  1'b0) ;
 g_cal D(  1'b0) ;

always @( negedge arc, posedge clk )
/* erasing all those line 
 case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

我将使用 if 和 else 结构,并使用 1'b1*/ 调用相应的实例

 // I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule
module fronter ( arc, length, clinic ) ;
 input [7:0] arc;
 output reg [7:0] length ;

 input [1:0] clinic;
 input en0, en1, en2, en3; // 11

 // clock generator  is here

 g_cal A( en0) ;
 g_cal B( en1) ;
 g_cal C( en2) ;
 g_cal D( en3) ;

always @( negedge arc, posedge clk )
  case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

// I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule

module g_cal ( en ) ;

 input en ;
 // some other jobs, calling another instances after making some job

endmodule

when I compile, compiler gives me ;

verilog.v:23: error: en0 is not a valid l-value in Numerator.
verilog.v:11:      : en0 is declared here as wire.
verilog.v:24: error: en1 is not a valid l-value in Numerator.
verilog.v:11:      : en1 is declared here as wire.
verilog.v:25: error: en2 is not a valid l-value in Numerator.
verilog.v:11:      : en2 is declared here as wire.
verilog.v:26: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
verilog.v:27: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
segmentation fault

How can I fix it ?
Why it gives error?

EDIT:
I have solved problem as ;

   // I erased that line "input en0, en1, en2, en3; // 11"

 // clock generator  is here

 g_cal A(  1'b0) ;
 g_cal B(  1'b0) ;
 g_cal C(  1'b0) ;
 g_cal D(  1'b0) ;

always @( negedge arc, posedge clk )
/* erasing all those line 
 case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

I will use if and else structure, and calling corresponding instance with 1'b1*/

 // I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule

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评论(2

岁月打碎记忆 2024-11-07 12:43:02

您正在尝试分配给输入(这很糟糕)。将输入 en0, en1, en2, en3; 更改为输出 reg en0, en1, en2, en3;reg 是必需的,因为您要在程序块内分配该变量(即alwaysinitial)。 “不是有效的左值”消息试图告诉您这一点。

另外,我假设 11、23、24 等是复制粘贴中的杂散行号......

You're trying assign to an input (which is bad). Change input en0, en1, en2, en3; to output reg en0, en1, en2, en3;. The reg is necessary since you are assigning to that variable within a procedural block (ie, an always or initial). The "not a valid l-value" message is trying to tell you this.

Also, I'm assuming that the 11, 23, 24, etc are stray line numbers from a copy-paste...

喜爱纠缠 2024-11-07 12:43:02

当我写的时候问题已经解决了;

reg en0, en1, en2, en3 ;

initial begin 
  en0 <= 1'b0; en1 <= 1'b0; 
  en2 <= 1'b0; en3 <= 1'b0;
end

g_cal A(  en0) ;
g_cal B(  en1) ;
g_cal C(  en2) ;
g_cal D(  en3) ;

@Marty 强调了重要的事情“reg 是必要的,因为您要在程序块中分配该变量(即,始终或初始)。”

Problem has solved when I write ;

reg en0, en1, en2, en3 ;

initial begin 
  en0 <= 1'b0; en1 <= 1'b0; 
  en2 <= 1'b0; en3 <= 1'b0;
end

g_cal A(  en0) ;
g_cal B(  en1) ;
g_cal C(  en2) ;
g_cal D(  en3) ;

@Marty have emphasized important thing "The reg is necessary since you are assigning to that variable within a procedural block (ie, an always or initial)."

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